Fritz J. Kub

Strain relaxation of SiGe islands on compliant oxide

The relaxation of patterned, compressively strained, epitaxial Si0.7Ge0.3 films transferred to borophosphorosilicate (BPSG) glass by a wafer-bonding and etch-back technique was studied as an approach for fabricating defect-free Si1−xGex relaxed films. Both the desired in-plane expansion and undesired buckling of the films concurrently contribute to the relaxation. Their relative role in the relaxation process was examined experimentally and by modeling. Using x-ray diffraction, Raman scattering and atomic force microscopy, the dynamics of in-plane expansion and buckling of Si0.7Ge0.3 islands for island sizes ranging from 10 μm×10 μm to 200 μm×200 μm for anneal temperatures between 750 and 800 °C was investigated. Lateral relaxation is favored in small and thick islands, and buckling is initially dominant in large and thin islands. Raising the temperature to lower viscosity of the oxide enhances the rate of both processes equally. For very long annealing times, however, the buckling disappeared, allowing l...

Cu 2 ZnSnS 4 polycrystalline thin films with large densely packed grains prepared by sol-gel method

Cu2ZnSnS4 (CZTS) was obtained from a sol-gel precursor which consists of copper chloride, zinc chloride, tin chloride, and thiourea. CZTS thin films were prepared by spin- coating the sol-gel precursor followed by annealing in a nitrogen atmosphere. The morphology, composition, and structure of the absorber layer were studied by scanning electron microscopy, energy dispersive spectroscopy, x-ray diffraction, and Raman scattering. The optical measure- ment shows the bandgap of these films is ∼1.51 eV, and the optical absorption coefficient is on the order of 10 4 cm −1 . CZTS solar cells with a structure of low-alkali glass/Mo/CZTS/CdS/i- ZnO/ZnO:Al/Al grid were tentatively fabricated. The best solar cell showed a short-circuit current density of 5.06 mA/cm 2 , an open-circuit voltage of 358 mV, a fill factor of 34.66%, and an efficiency of 0.63% under AM1.5 (100 mW/cm 2 ) illumination. These results demonstrate the CZTS thin films were successfully deposited by a cheap sol-gel technique. C 2011 Society of

Ultrathin strained-SOI by stress balance on compliant substrates and FET performance

Ultrathin, strained-silicon-on-insulator (s-SOI) structures without a residual silicon-germanium (SiGe) underlayer have been fabricated using stress balance of bi-layer structures on compliant borophosphorosilicate glass (BPSG). The bi-layer structure consisted of SiGe and silicon films, which were initially pseudomorphically grown on a silicon substrate and then transferred onto BPSG by a wafer bonding and SmartCut process. The viscous flow of the BPSG during a high-temperature anneal then allowed the SiGe/Si bi-layer to laterally coherently expand to reach stress balance, creating tensile strain in the silicon film. No dislocations are required for the process, making it a promising approach for achieving high-quality strained-silicon for device applications. To prevent the diffusion of boron and phosphorus into the silicon from the BPSG, a thin nitride film was inserted between the bi-layer and BPSG to act as a diffusion barrier, so that a lightly doped, sub-10-nm s-SOI layer (0.73% strain) was demonstrated. N-channel MOSFETs fabricated in a 25-nm silicon layer with 0.6% strain showed a mobility enhancement of 50%.

Buckling suppression of SiGe islands on compliant substrates

A cap layer was used to suppress buckling during the relaxation of compressively strained 30 nm Si0.7Ge0.3 islands on borophosphorosilicate glass. The lateral expansion and buckling of a bilayer structure made of SiGe and a cap layer were studied by both modeling and experiment. Both epitaxial silicon and amorphous silicon dioxide (SiO2) caps were investigated. Caps stiffen the islands to reduce buckling and accelerate the lateral relaxation, so that larger, flat, relaxed SiGe islands can be achieved. Using a 31 nm silicon cap, flat Si 0.7Ge0.3 islands up to 200 mm3200mm were achieved. However, germanium diffusion in the SiGe/Si structure took place during relaxation anneals and lowered the germanium fraction of the final fully relaxed SiGe film. Silicon dioxide caps, which are not prone to germanium diffusion, allowed suppression of SiGe buckling without lowering the germanium percentage. Full relaxation of SiGe islands was achieved by a controlled multicycle silicon dioxide removal and anneal procedure. Large, fully relaxed, smooth SiGe islands obtained using cap layers indicate that this approach could be of potential use for electronic device applications.

Strain partition of Si/SiGe and SiO2/SiGe on compliant substrates

Strain partitioning of crystalline Si and amorphous SiO2 deposited on crystalline SiGe on a compliant viscous borophosphorosilicate (BPSG) glass has been observed. Pseudomorphic epitaxial Si was deposited on SiGe films, which were fabricated on BPSG by wafer bonding and the Smart-cut® process. The strains in SiGe and Si films were found to change identically during a high-temperature anneal which softened the BPSG film, indicating a coherent interface between SiGe and Si films and precluding slippage or the formation of misfit dislocations along the interface. The stress balance between the layers dictated the final state, which confirmed that BPSG was a perfectly compliant substrate and did not exert any force on the layers above it. Similar results were found for amorphous SiO2 deposited on SiGe on BPSG and then annealed. This shows that the viscous BPSG is an effective compliant substrate for the strain engineering of elastic films without the introduction of dislocations.

Reduced Self-Heating in AlGaN/GaN HEMTs Using Nanocrystalline Diamond Heat-Spreading Films

Nanocrystalline diamond (NCD) thin films are deposited as a heat-spreading capping layer on AlGaN/GaN HEMT devices. Compared to a control sample, the NCD-capped HEMTs exhibited approximately 20% lower device temperature from 0.5 to 9 W/mm dc power device operation. Temperature measurements were performed by Raman thermography and verified by solving the 2-D heat equation within the device structure. NCD-capped HEMTs exhibited 1) improved carrier density <i>NS</i>, sheet resistance <i>R</i>_SH; 2) stable Hall mobility μ<i>H</i> and threshold voltage <i>VT</i>; and 3) degraded on-state resistance <i>RON</i> , contact resistance <i>RC</i>, transconductance <i>Gm</i>, and breakdown voltage <i>V</i>_BR.

Fully-depleted strained-Si on insulator NMOSFETs without relaxed SiGe buffers

Fully-depleted strained Si n-channel MOSFETs were demonstrated on a compliant borophosphorosilicate insulator (BPSG) without an underlying SiGe buffer layer. Stress balance of a SiGe/Si structure, transferred onto BPSG by wafer bonding and Smart-cut processes, is utilized for the first time to make strained-Si on insulator (sSOI) by a process that does not involve the introduction of misfit dislocations. Strained-Si n-channel MOSFETs with a strain level of 0.6%, equivalent to that of a conventional strained Si layer grown on a relaxed Si/sub 0.85/Ge/sub 0.15/ buffer, exhibit 60% mobility enhancement over the control, in good agreement with theory. This approach to fabricating strained Si overcomes any potential process or device complexity due to the presence of a SiGe layer in the final devices.

Improved Low-Temperature Si ­ Si Hydrophilic Wafer Bonding

Low-temperature processing is important for bond and exfoliation and materials integration techniques. Of particular importance for hydrophilic wafer bonding is the reduction and removal of thermally generated voids at the bond interface, i.e., voids not caused by particulates. Possible causes of thermally generated voids are excess water and hydrocarbon contamination, both at the bond interface. Several bonding preparation techniques were explored, and the effects on interfacial void density and bond strength were recorded. After bonding, all wafer pairs were annealed to 250°C. Infrared imaging was used to monitor void formation, and bond strength was measured using the blade insertion method. Microvoids with lateral dimensions greater than 30 μm were imaged using acoustic microscopy. The highest bond strength was 1260 mJ/m 2 for plasma-cleaned wafers followed closely by 1150 mJ/m 2 for an HF oxide strip before hydrophilization. In addition to these techniques, bonding in a vacuum or the use of a prebond anneal were able to eliminate interfacial voids up to the anneal temperature.

A Si0.7Ge0.3 strained‐layer etch stop for the generation of thin layer undoped silicon

The use of a Si0.7Ge0.3 strained layer as an etch stop in silicon‐based materials is reported. The etch rates were characterized through silicon and a 60 nm Si0.7Ge0.3 strained layer. The etch rate through undoped silicon was 17–20 nm/min, while the etch rate through the Si0.7Ge0.3 layer was 1 nm/min. After annealing the wafer to 850 °C for 30 min, transmission electron microscopy was used to show that strain in the alloy layer was only partially relieved, and that generated misfit dislocations were confined to the strained Si0.7Ge0.3 layer. The etch rate through the strained layer increased to 1.7 nm/min after this treatment, and was still perfectly functional as an etch stop.

Characterization of Si pn junctions fabricated by direct wafer bonding in ultra-high vacuum

The electrical characteristics of pn junctions formed by direct bonding of silicon wafers in ultra-high vacuum have been quantified. The bonding process produces low reverse leakage <1 μA/cm2 and near-ideal forward current. The observation of bulk-like bonded interfaces is supported by transmission electron microscopy and infra-red transmission imaging.