Karl D. Hobart

Room temperature operation of epitaxially grown Si/Si0.5Ge0.5/Si resonant interband tunneling diodes

Resonant interband tunneling diodes on silicon substrates are demonstrated using a Si/Si0.5Ge0.5/Si heterostructure grown by low temperature molecular beam epitaxy which utilized both a central intrinsic spacer and δ-doped injectors. A low substrate temperature of 370 °C was used during growth to ensure a high level of dopant incorporation. A B δ-doping spike lowered the barrier for holes to populate the quantum well at the valence band discontinuity, and an Sb δ-doping reduces the doping requirement of the n-type bulk Si by producing a deep n+ well. Samples studied from the as-grown wafers showed no evidence of negative differential resistance (NDR). The effect of postgrowth rapid thermal annealing temperature was studied on tunnel diode properties. Samples which underwent heat treatment at 700 and 800 °C for 1 min, in contrast, exhibited NDR behavior. The peak-to-valley current ratio (PVCR) and peak current density of the tunnel diodes were found to depend strongly on δ-doping placement and on the annea...

Strain relaxation of SiGe islands on compliant oxide

The relaxation of patterned, compressively strained, epitaxial Si0.7Ge0.3 films transferred to borophosphorosilicate (BPSG) glass by a wafer-bonding and etch-back technique was studied as an approach for fabricating defect-free Si1−xGex relaxed films. Both the desired in-plane expansion and undesired buckling of the films concurrently contribute to the relaxation. Their relative role in the relaxation process was examined experimentally and by modeling. Using x-ray diffraction, Raman scattering and atomic force microscopy, the dynamics of in-plane expansion and buckling of Si0.7Ge0.3 islands for island sizes ranging from 10 μm×10 μm to 200 μm×200 μm for anneal temperatures between 750 and 800 °C was investigated. Lateral relaxation is favored in small and thick islands, and buckling is initially dominant in large and thin islands. Raising the temperature to lower viscosity of the oxide enhances the rate of both processes equally. For very long annealing times, however, the buckling disappeared, allowing l...

Low-temperature cleaning processes for Si molecular beam epitaxy

Hydrogen‐terminated surface cleaning techniques of silicon substrates were investigated by using x‐ray photoelectron spectroscopy (XPS), secondary ion mass spectrometry (SIMS), and transmission electron microscopy (TEM). Either a 4% HF dip or an HF‐terminated abbreviated Shiraki clean was used as the cleaning technique. Shiraki‐cleaned samples were grown as control samples. XPS was used to measure the C, O, and F remaining on the surface at various stages of the cleaning/growth process, including after a 1 h bake at 200 °C prior to growth. XPS did not detect a significant difference in the adsorbate concentrations between the baked and unbaked samples. From SIMS, the lowest impurity concentrations at the epitaxial/substrate interface were achieved with the abbreviated Shiraki clean, approximately at the same levels as obtained with the standard Shiraki clean, 1.3×1013, 5.4×1012, 1.6×1010, and 4.2×1011/cm2 for C, O, F, and N, respectively. This was achieved without the 850 °C anneal required to desorb the ...

Surface segregation and structure of Sb-doped Si(100) films grown at low temperature by molecular beam epitaxy

Abstract Sb surface segregation and doping during Si(100) molecular beam epitaxy were studied for growth temperatures of 320–500°C. Surface segregation was analyzed by depth profiling with secondary ion mass spectrometry and the results indicate the existence of several distinct dopant concentration- and temperature-dependent surface segregation regimes: (1) For dilute Sb surface concentrations the measurements reveal a region where bulk and surface concentrations are linearly related, and the surface segregation is described by a constant. However, the experimentally determined temperature dependence of the segregation does not follow simple kinetics theory, and appreciable surface segregation is observed at temperatures ≤ 400°C. (2) At temperatures ≥ 350°C, the surface segregation reaches a maximum for Sb surface concentrations of 0.5 monolayers. (3) For surface concentrations near 1 monolayer, the surface segregation decreases with increasing surface Sb coverage due to dopant interaction within surface and subsurface layers. In cases where films were grown under very high dopant fluxes, we have identified cone-like defects and stacking faults that are the result of the apparent surface concentration exceeding 1 monolayer.

Ultrathin strained-SOI by stress balance on compliant substrates and FET performance

Ultrathin, strained-silicon-on-insulator (s-SOI) structures without a residual silicon-germanium (SiGe) underlayer have been fabricated using stress balance of bi-layer structures on compliant borophosphorosilicate glass (BPSG). The bi-layer structure consisted of SiGe and silicon films, which were initially pseudomorphically grown on a silicon substrate and then transferred onto BPSG by a wafer bonding and SmartCut process. The viscous flow of the BPSG during a high-temperature anneal then allowed the SiGe/Si bi-layer to laterally coherently expand to reach stress balance, creating tensile strain in the silicon film. No dislocations are required for the process, making it a promising approach for achieving high-quality strained-silicon for device applications. To prevent the diffusion of boron and phosphorus into the silicon from the BPSG, a thin nitride film was inserted between the bi-layer and BPSG to act as a diffusion barrier, so that a lightly doped, sub-10-nm s-SOI layer (0.73% strain) was demonstrated. N-channel MOSFETs fabricated in a 25-nm silicon layer with 0.6% strain showed a mobility enhancement of 50%.

Buckling suppression of SiGe islands on compliant substrates

A cap layer was used to suppress buckling during the relaxation of compressively strained 30 nm Si0.7Ge0.3 islands on borophosphorosilicate glass. The lateral expansion and buckling of a bilayer structure made of SiGe and a cap layer were studied by both modeling and experiment. Both epitaxial silicon and amorphous silicon dioxide (SiO2) caps were investigated. Caps stiffen the islands to reduce buckling and accelerate the lateral relaxation, so that larger, flat, relaxed SiGe islands can be achieved. Using a 31 nm silicon cap, flat Si 0.7Ge0.3 islands up to 200 mm3200mm were achieved. However, germanium diffusion in the SiGe/Si structure took place during relaxation anneals and lowered the germanium fraction of the final fully relaxed SiGe film. Silicon dioxide caps, which are not prone to germanium diffusion, allowed suppression of SiGe buckling without lowering the germanium percentage. Full relaxation of SiGe islands was achieved by a controlled multicycle silicon dioxide removal and anneal procedure. Large, fully relaxed, smooth SiGe islands obtained using cap layers indicate that this approach could be of potential use for electronic device applications.

Strain partition of Si/SiGe and SiO2/SiGe on compliant substrates

Strain partitioning of crystalline Si and amorphous SiO2 deposited on crystalline SiGe on a compliant viscous borophosphorosilicate (BPSG) glass has been observed. Pseudomorphic epitaxial Si was deposited on SiGe films, which were fabricated on BPSG by wafer bonding and the Smart-cut® process. The strains in SiGe and Si films were found to change identically during a high-temperature anneal which softened the BPSG film, indicating a coherent interface between SiGe and Si films and precluding slippage or the formation of misfit dislocations along the interface. The stress balance between the layers dictated the final state, which confirmed that BPSG was a perfectly compliant substrate and did not exert any force on the layers above it. Similar results were found for amorphous SiO2 deposited on SiGe on BPSG and then annealed. This shows that the viscous BPSG is an effective compliant substrate for the strain engineering of elastic films without the introduction of dislocations.

Relaxation of compressed elastic islands on a viscous layer

A recent technique can fabricate SiGe thin film islands on a glass layer, which itself lies on a silicon wafer. The islands initially have an inplane compressive strain. Upon annealing, the glass flows, and the islands relax. The resulting strain-free islands are used as substrates to grow epitaxial optoelectronic devices. This paper models the annealing process. A small island relaxes by inplane expansion. The glass being viscous, the relaxation starts at the island edges, and propagates to the island center. A large island, however, wrinkles at the center before the inplane relaxation arrives. Further annealing gives rise to one of two outcomes. The wrinkles may disappear when the inplane relaxation arrives, leading to a flat, strain-free island. Alternatively, the wrinkles may cause significant tensile stress in the island, leading to fracture. We model the island by the von Karman plate theory, and the glass layer by the Reynolds lubrication theory. The solid and the fluid couple at the interface by the continuous traction and displacement. Numerical simulations evolve the inplane expansion and the wrinkles simultaneously. We determine the critical island size, below which inplane expansion prevails over wrinkling. This critical island size depends on several experimental variables, and is much larger than the Euler buckling wavelength.

Reduced Self-Heating in AlGaN/GaN HEMTs Using Nanocrystalline Diamond Heat-Spreading Films

Nanocrystalline diamond (NCD) thin films are deposited as a heat-spreading capping layer on AlGaN/GaN HEMT devices. Compared to a control sample, the NCD-capped HEMTs exhibited approximately 20% lower device temperature from 0.5 to 9 W/mm dc power device operation. Temperature measurements were performed by Raman thermography and verified by solving the 2-D heat equation within the device structure. NCD-capped HEMTs exhibited 1) improved carrier density <i>NS</i>, sheet resistance <i>R</i>_SH; 2) stable Hall mobility μ<i>H</i> and threshold voltage <i>VT</i>; and 3) degraded on-state resistance <i>RON</i> , contact resistance <i>RC</i>, transconductance <i>Gm</i>, and breakdown voltage <i>V</i>_BR.

Fully-depleted strained-Si on insulator NMOSFETs without relaxed SiGe buffers

Fully-depleted strained Si n-channel MOSFETs were demonstrated on a compliant borophosphorosilicate insulator (BPSG) without an underlying SiGe buffer layer. Stress balance of a SiGe/Si structure, transferred onto BPSG by wafer bonding and Smart-cut processes, is utilized for the first time to make strained-Si on insulator (sSOI) by a process that does not involve the introduction of misfit dislocations. Strained-Si n-channel MOSFETs with a strain level of 0.6%, equivalent to that of a conventional strained Si layer grown on a relaxed Si/sub 0.85/Ge/sub 0.15/ buffer, exhibit 60% mobility enhancement over the control, in good agreement with theory. This approach to fabricating strained Si overcomes any potential process or device complexity due to the presence of a SiGe layer in the final devices.