Fu-Chien Chiu

Reliability characteristics and conduction mechanisms in resistive switching memory devices using ZnO thin films

In this work, bipolar resistive switching characteristics were demonstrated in the Pt/ZnO/Pt structure. Reliability tests show that ac cycling endurance level above 106 can be achieved. However, significant window closure takes place after about 102 dc cycles. Data retention characteristic exhibits no observed degradation after 168 h. Read durability shows stable resistance states after 106 read times. The current transportation in ZnO films is dominated by the hopping conduction and the ohmic conduction in high-resistance and low-resistance states, respectively. Therefore, the electrical parameters of trap energy level, trap spacing, Fermi level, electron mobility, and effective density of states in conduction band in ZnO were identified.

Conduction mechanism of resistive switching films in MgO memory devices

In this work, nonpolar resistance switching behavior was demonstrated in Pt/MgO/Pt structure. The resistance ratio of high resistance state (HRS) and low resistance state (LRS) is about on the order of 105 for the compliance current (Icomp) of 1 mA at 300u2009K. Using enough Icomp (≥0.5 mA) during SET processes, the LRS resistances reach a minimum of about 102–103 Ω and the RESET currents reach a maximum of about 10−4–10−3 A. Experimental results indicate that the conduction mechanism in MgO films is dominated by the hopping conduction and the Ohmic conduction in HRS and LRS, respectively. Therefore, the electrical parameters of trap energy level, trap spacing, Fermi level, electron mobility, and effective density of states in conduction band in MgO films were obtained.

An SCR-Incorporated BJT Device for Robust ESD Protection With High Latchup Immunity in High-Voltage Technology

A silicon-controlled rectifier (SCR)-incorporated BJT with high holding voltage is developed for electrostatic discharge (ESD) protection in a 0.6 μm high-voltage 10 V process. This device consists simply of a floating P+ diffusion incorporated in a parasitic NPN BJT. A robust 6-7 kV ESD threshold and high-latchup-immune holding voltage of 15-18 V can be achieved by layout optimization of the NPN-N+ -collector to floating P+ -diffusion spacing and the floating P+ diffusion width. It can be equivalently regarded as parallel connection of an incorporated PNPN SCR part and an NPN BJT part. The incorporated SCR part is further composed of a parasitic SCR in series with a reverse-biased PN diode formed by the floating P+ region and N-well. The further analysis shows that the floating P+ diffusion is the key part of this SCR-incorporated BJT. The parasitic reverse-biased PN diode sustains most of the high holding voltage. The parasitic NPN BJT plays a major role in ESD current conduction, while the incorporated SCR in series with the reverse-biased PN diode is the secondary conduction path.

Design optimization of ESD protection and latchup prevention for a serial I/O IC

ESD/latchup are often two contradicting variables during IC reliability development. Trade-off between the two must be properly adjusted to realize ESD/latchup robustness of IC products. A case study on SERIAL Input/Output (I/ O) IC’s is reported here to reveal this ESD/latchup optimization issue. SERIAL I/O IC features a special clamping property to wake up PC’s during system standby situation. Along with high voltage operation, Input/Output (I/O) protection design of this IC becomes one of the most challenging tasks in the product reliability development. In the initial development phase, ignorance of latchup susceptibility resulted in severe Electrical Overstress (EOS) damage during latchup tests, and also gave a false over estimate of ESD protection threshold through parasitic latchup paths. The latchup origin is an output PMOS and floating-well ESD triggering NMOS beside the PMOS, and the main fatal link is this high-voltage (HV) NMOS connecting to a bi-directional SCR cell. This fatal link led to totally five latchup sites and three latchup paths clarified through careful and intensive FIB failure analysis, while this powerful SCR ESD device without appropriate triggering mechanism still could not provide sufficient product-level ESD hardness. Owing to there being no design window between ESD and latchup, the original several protection schemes were all abandoned. Using this bi-directional SCR ESD cell and proper triggering PNP bipolar transistors, a new I/O protection circuit could sustain at least ESD/HBM 4 kV and latchup triggering current 150 mA tests, thus accomplish the best optimization of ESD/latchup robustness.

ESD and Latchup Optimization of an Embedded-Floating-pMOS SCR-Incorporated BJT

This paper develops optimization between electrostatic discharge (ESD) and latchup characteristics for a silicon-controlled rectifier (SCR)-incorporated Bipolar Junction Transistor (BJT) in a 0.18-μm, 3.3 V process. This device is composed of a floating pMOSFET embedded in a parasitic n-well/p-sub/n+ region BJT structure. The floating pMOS gate is further coupled with an RC network for controlling its switching. The floating pMOS could increase the effective width of its floating p+ region to enhance ESD robustness during ESD zapping events, whereas maintain its floating p+ region narrower during IC operation situation. With the optimized structure dimensions, this device can reach transmission-line pulse second breakdown current 6 A, ESD/ human-body model over 8 kV, which are the same as those of an SCR, and its latchup trigger current is at least 1.9 times greater.

A SCR-buried BJT device for robust ESD protection with high latchup immunity in high-voltage technology

An SCR-buried BJT with a high holding voltage is developed for ESD protection in a 0.6 µm high voltage 10V process. This device simply consists of a floating P⁺ diffusion buried in a parasitic NPN BJT. A robust 6∼7KV ESD threshold and high-latchup-immune 15∼18V holding voltage can be achieved by layout optimization of the anode-to-floating- P⁺-diffusion spacing and this P⁺ diffusion width.

Anomalous latchup failure induced by on-chip ESD protection circuit in a high-voltage CMOS IC product

Latchup failure induced by ESD protection circuits occurred in a high-voltage IC product. Latchup occurred anomalously at only several output pins. All output pins have nearly identical layouts except the side output pin has a N-well resistor of RC gate-coupled PMOS beside. It was later found this N-well resistor is the main cause of inducing latchup.

A Split Island Layout Style of Butting/Inserted Substrate Pickups for NMOSFET ESD Reliability

Butting/inserted pickup layout style could result in severe ESD degradation of NMOS devices beyond deep submicron technology. A split island layout style of butting/inserted substrate pickups is designed for a multifinger NMOS structure to enhance its ESD reliability. This layout style divides the substrate pickup diffusion bands along the whole polygate finger direction into segmented diffusion islands in the source area. This layout technique could improve the TLP second breakdown current of the 1.8u2009V butting pickup structure by 58~66% and 1.8u2009V/3.3u2009V inserted pickup case by 2.8 times. This style also shows excellent enhancement for the ESD/HBM levels of the 1.8u2009V and 3.3u2009V butting pickup case by 2.1~2.3 times and 18%~6 times, respectively, and the 1.8u2009V and 3.3u2009V inserted pickup case by 2.4~2.9 times and 13%~6 times, respectively. This simple technique could restore the ESD threshold level of the butting/inserted pickup layout style back to that of the normal GGNMOS without any further area consumption or fabrication cost.

Reliability characteristics of cerium dioxide thin films

The reliability characteristics of CeO<inf>2</inf> thin films were studied. During stressing, stress-induced leakage current and charge trapping are dominant at low field and high field, respectively. The trap capture cross-sections are extracted to be around 5.7×10⁻¹⁹ cm² and 3.5×10⁻¹⁴ cm² in the event of “stressing” and “breakdown”, respectively.

Inserted substrate pickup style with external resistance in an ESD NMOS transistor

Butting and inserted pickup layout in MOSFETs leads to substrate resistance shunting effect and serious ESD robustness degradation. This work develops novel layout with external well/ diffusion resistance embedding between the substrate and the grounding terminal in the NMOS transistors. This layout method can greatly enhance ESD performance of the inserted pickup devices. The second breakdown current of the 1.8V cases improves by 2.7∼2.9 times, ESD/HBM threshold increases by 2.3∼3.2 times; and the second breakdown current of the 3.3V condition raises by 2.2 times, ESD/ HBM threshold even rises by 10 times.