Jen-Chou Tseng

An ultra-low power K-band low-noise amplifier co-designed with ESD protection in 40-nm CMOS

This paper presents a K-band low noise amplifier (LNA) co-designed with ESD protection circuit in 40-nm CMOS technology. By treating ESD devices as a part of the input matching network, an ESD protected 24-GHz LNA is demonstrated with a NF of 3.2 dB under a power consumption of only 4.1 mW. The ESD protection network is composed of dual-diode and a gate-driven power clamp achieving an ESD level of 2.8 kV human body model (HBM). Owing to the co-design approach, the NF only degrades by 0.2 dB compared with the reference LNA without the ESD network. The ESD-LNA presents a power gain of 13.0 dB with the input and output return losses both greater than 10 dB. To the best of our knowledge, this is the first report on a 24-GHz ESD-protected LNA in 40-nm CMOS.

A 6.5kV ESD-protected low noise amplifier in 65-nm CMOS

A new ESD topology is proposed for RF low-noise amplifier (LNA). By using the modified silicon-controlled rectifier (MSCR) in conjunction with a P+/N-well diode clamp, a 5.8-GHz LNA with 6.5-kV ESD protection circuit is demonstrated by a 65-nm CMOS technology. Compared with the reference design, the new topology enhances the ESD level from 3.5 kV to 6.5 kV for human body model (HBM) while the noise figure (NF) is only 0.13 dB higher. Under a supply voltage of 1.2 V and drain current of 6.5 mA, the proposed ESD-protected LNA has a NF of 2.57 dB with an associated power gain of 16.7 dB. The input third-order intercept point (IIP3) is −11 dBm and the input and output return losses are below −15.9 dB and −20 dB, respectively.

An on-chip combo clamp for surge and universal ESD protection in bulk FinFET technology

A surge protection consisted of the ready-made ESD clamp transistors has been designed and characterized in FINFET technology. It can endure all the stresses from CDM, HBM and Surge events. Compared to a conventional 0.7V RC-based core ESD clamp, the proposed cell greatly boosts the Surge immunity from 4V to 19V.

An analog front-end circuit with dual-directional SCR ESD protection for UHF-band passive RFID tag

In this study, we demonstrate an analog front-end (AFE) circuit with ESD protection for a passive RFID tag at UHF-band (860∼960 MHz) in a 0.18-μm CMOS technology. A dual-directional silicon-controlled-rectifier (dual-SCR) structure is proposed for the ESD protection under the large-signal operation at the RFID input. With the well-designed dual-SCR, a large trigger voltage (VT) of ∼ 16.9 V is obtained. The parasitic capacitance of the ESD block is only ∼ 34 fF, which has virtually no impact on the core circuits at the frequency of interest. The measured ESD levels achieve 3.0-kV human-body-mode (HBM) and 200-V machine-mode (MM), respectively. The RF-DC rectifier in the RFID circuit can generate a stable power supply output about 1.2 V when the RF input power exceeds −7.5 dBm.

Investigation and solution to the early failure of parasitic NPN triggered by the adjacent PNP ESD clamps

The mechanism of PNP-triggered parasitic NPNs early failure during ESD stress has been clarified for the first time. We proposed two solutions for the high ESD and Latchup-hard requirements. The embedded SCR structure provides high HBM immunity, which can serve pin-to-pin protection such as the differential IO application. For the Latchup-hard solution, a sandwich guard ring structure solves the snapback-induced local ESD damage issue and achieves low substrate current injection. Note that the spacing rule for the parasitic NPN structures is also greatly reduced up to 44.7%.