Fu-Chiung Cheng

Self-timed carry-lookahead adders

Integer addition is one of the most important operations in digital computer systems because the performance of processors is significantly influenced by the speed of their adders. This paper proposes a self-timed carry-lookahead adder in which the logic complexity is a linear function of n, the number of inputs, and the average computation time is proportional to the logarithm of the logarithm of n. To the best of our knowledge, our adder has the best area-time efficiency which is /spl Theta/(nloglogn). An economic implementation of this adder in CMOS technology is also presented. SPICE simulation results show that, based on random inputs, our 32-bit self-timed carry-lookahead adder is 2.39 and 1.42 times faster than its synchronous counterpart and self-timed ripple-carry adder, respectively, and, based on statistical data gathered from a 32-bit ARM simulator, it is 1.99 and 1.83 times faster than its synchronous counterpart and self-timed ripple-carry adder, respectively.

Practical design and performance evaluation of completion detection circuits

To achieve the goal of designing high performance self-timed circuits, one of the key factors is to design a fast completion detection circuit, detecting the completion of the self-timed circuit. Some recent work proposed by Wuu and Yun on completion detection circuits is reviewed. A new design of high performance completion detection circuits for dual-rail self-timed circuits is presented. The results of our SPICE simulation show that our computation-completion detection circuit is more than 9 times faster than Wuus and Yuns, and our reset-completion detection circuits is 2.7 times faster than Wuus.

Delay-insensitive carry-lookahead adders

Integer addition is one of the mast important operations in digital computer systems because the performance of processors is significantly influenced by the speed of their adders. This paper proposes a delay insensitive, carry-lookahead adder in which the logic complexity is a linear function of n, the number of inputs, and the average computation time is proportional to the logarithm of the logarithm of n. We also show an economic implementation of this adder in CMOS technology.

Efficient systematic error-correcting codes for semi-delay-insensitive data transmission

A lot of papers have been written on error correcting/detecting codes for data transmission, but none of the codes are designed to address error correction for delay-insensitive or semi-delay-insensitive (SDI) data transmission. In this paper we address the problem of SDI communication where errors may occur during transmission or encoding. Three error models for SDI data transmission are defined and the general solution schemes for these models are proposed. An efficient systematic SDI error-correcting code for the four-phase handshaking protocol is designed to solve one asymmetric error model. Our code is efficient in terms of encoding, decoding and completion checking. The novelty of our SDI error-correcting code is that our code can correct errors and detect completion at the same time in SDI data transmission. The proposed schemes are particularly suitable for deep-submicron and high-speed board design.

Synthesis of asynchronous circuits for stuck-at and robust path delay fault testability

In this paper, we present methods for synthesizing multilevel asynchronous circuits to be both hazard free and completely testable. Making an asynchronous two-level circuit hazard free usually requires the introduction of either redundant or nonprime cubes or both. This adversely affects the circuits testability. However, using extra inputs, which is seldom necessary, and a synthesis-for-testability method, we convert the two-level circuit into a multilevel circuit that is completely testable. To avoid the addition of extra inputs as much as possible, we introduce new exact minimization algorithms for hazard-free two-level logic where we first minimize the number of redundant cubes and then minimize the number of nonprime cubes. We target both the stuck-at and robust path delay fault models using similar methods. However, the area overhead for the latter may be slightly higher than for the former.

Synthesis of QDI FSMs from Synchronous Specifications

Quasi-Delay insensitive (QDI) circuits are the most robust and practical that can be built and are resilient to process, temperature and voltage (PVT) variations. Although there are many research papers that can translate synchronous designs into asynchronous sequential designs, to the best of our knowledge, there is neither QDI finite state machine (FSM) models proposed nor algorithms or tools designed. Three QDI FSM (QFSM) designs (i.e. NCLD, NCLX and ROC QFSMs) are proposed and an algorithm to automatically synthesize QFSMs from synchronous FSM specifications in Verilog is designed and implemented in Java. One of the distinguish feature is that the behaviors of our QFSMs are the same as those of the corresponding synchronous FSMs in terms of functionality. This greatly simplifies the verification complexity and reduces verification cost. Two sets of FSM circuits (i.e. verifiable benchmark circuits and ISCAS89) are exploited to carry out verification and performance evaluation. The experimental results show that ROCopt QFSMs use the least hardware cost and consume lowest energy in average.

Design and implementation of Web service integration tool

WWW (World Wide Web) has become the richest resource pool of services and information. But most of services (e.g. real time stock quote information and Web mail service) are independent and distributed. If we need a new Web service that sends us an email when some stock quote reaches a specific price, a Web service integration tool is needed to compose the Web stock quote information with the Web mail service. This paper proposes a convenient and powerful integration tool to seamlessly integrate the existing Web services into new services. Our tool, called Web service integration tool (WSIT), provides the functionalities to record and modulize existing Web services, to design, modify and compose recorded Web services, and to play and test the new composed Web services.

Automatic synthesis of composable sequential quantum Boolean circuits

This paper presents a methodology to transfer self-timed circuit specifications into sequential quantum Boolean circuits (SQBCs) and composable SQBCs (CQBCs). State graphs (SGs) are used to describe the behaviors of self-timed circuits and then are translated into SQBCs based on Toffoli gates. The concept of IP (intellectual property) reuse is applied to the constructed SQBCs to produce reusable and composable quantum Boolean circuits (CQBCs). Therefore, these reusable CQBCs as basic modular components can be exploited to construct more complicated quantum Boolean circuits. A set of self-timed components is successfully and automatically synthesized into CQBCs by our methodology. These CQBCs can be used as building blocks to compose control-path components of self-timed systems.

Robust Visual Mouse by motion history image

A real time V shape hand gesture recognition system by motion history template matching is proposed in this paper. Initially, user moves one of his/her hands in a specified region for template setup. Then, possible moving hand regions can be extracted by overlapping motion masks and skin color image. After noise removal of these regions, motion history template matching is used to recognize the V shaped hand gesture for shape toleration. The valley point of V is used to navigate the cursor and the left/right fingertip defines the left/right mouse button. In experiments, users can operate the windows system without physically contacting any equipment. The processing speed is more than 30 fps for images of size 320*240. The accuracy rate for the V shape hand gesture recognition is 96.92%. As to the recognition rates for left click, right click, and double click, we have 100%, 100%, and 91.53%, respectively.

A low-latency GALS interface implementation

With the VLSI technology improving rapidly, SoC has been becoming the most important VLSI application. However, clock distribution and low power have already become the two most important issues in SoC design. In addition, its also a very important issue to integrate IPs that can perform operations correctly with different clocks. Asynchronous circuits may resolve these problems by removing the “clock” signal. But its too hard to implement the whole circuits with asynchronous circuit. The GALS (Globally-Asynchronous Locally-Synchronous) design methodology can balance this problem via separating each synchronous design with asynchronous interface. Thus, each part of the circuit can perform operations with its own clock. The communication between different parts of the circuit can be achieved via asynchronous channels. The GALS provides a reliable communication between different modules. However, the latency of GALS interface may cause performance degradation seriously. Thus how to reduce the latency of GALS interface is significant. In this paper, we implemented a small and simple stretchable-clock based GALS wrapper with low-latency in Verilog HDL and synthesized the design with TSMC 0.13µm cell library. We also showed that the wrapper can operate correctly with modules which operate with great different clock frequencies. In addition, we also recommend adding FIFO storage element on the transmission path.