Shu-Ming Chang

Reliability tests for a three dimensional chip stacking structure with through silicon via connections and low cost

In order to achieve the shorter circuit design of multiple chips, three-dimensional (3D) packaging technologies with through silicon vias were developed to achieve high performance, low power consumption and small packaging size. In this paper, a PCB (Printed Circuit Board) processing compatible structure of three-dimensional chip stacking with low cost and easy fabrication will be shown. 3D and through Si via connections were formed by UV laser drilling technology. Laser drilling is a non-contact manufacture method and laser beam with high energy can be focused to a small spot (15 mum beam diameter) for material ablating and removing without mask used. Several processes are the keys to accomplish 3D stacking, such as wafer thinning process, through silicon via forming process, dielectric layer forming process, metallization process, and inter chips bonding process. By integration of the mentioned key processes, a 3D chip stacking structure with 10 layers was carried out. The thickness of chip was 100 mum. Daisy chain pattern was designed for the electrical measurement of 3D stacking structure. The testing results show that the resistance of multi- chip stacking structure is about 0.056 Omega/cm. Some reliability test, such as temperature cycling test and pressure cooker test were also done. These testing results verified this PCB processing compatible 3D chip stacking technology with low cost is a reliable structure for 3D SiP (System in Packaging) module application.

Investigations of strength of copper-bonded wafers with several quantitative and qualitative tests

The strengths of Cu-bonded wafers with respect to different bonding temperatures and bonding durations by quantitative and qualitative approaches were reviewed and investigated. These investigations include the mechanical dicing test, the tape test, the pull test, and the push test. For all test results, the strength of Cu-bonded wafers increases with increases in bonding duration or bonding temperature. Thermal anneal after bonding improved the bonding strength only at the high bonding temperature and not at the low temperature.

Development and characterization of rigid-flex interface

Flat panel displays (FPDs) are now getting more important role in the application of digital home and personal consumer electronics. For the future mobile application, the lack of flexibility and the decrement of weight will become the major challenges by using the glass substrate. The new choice of substrate material can provide the benefits to make the display become flexible that the current glass substrate is hard to compete with. Herein, we focused on the packaging approach by adopting the newly development technology of rigid-flex packaging by introducing flexible interconnect. There are two packaging approaches we explore the concept for flexible FPDs. One is the stretchable interconnect and the other is ultra thin die attached method. The results show we can achieve the 25% stretchable metal trace on flexible substrate, such as PU or PDMS and the resistance is keeping as low as 5 ohm/cm without any deformation. Besides, by choosing the suitable adhesives, we can also demonstrate the strong reliable interface during the bending test. The reliability test shows the intriguing structure can be applied for the flexible panel displays

A novel crack and delamination protection mechanism for a WLCSP using soft joint technology

Purpose – The coefficient of thermal expansion (CTE) mismatch between silicon and organic printed circuit board (PCB) materials causes a reliability issue for ball grid array type electronic packages. This makes it difficult for conventional wafer level chip scaled packaging (WLCSP) with large die to satisfy the reliability requirements. Therefore, in this study a novel solder joint protection‐WLCSP (SJP‐WLCSP) structure is proposed to overcome the reliability issue.Design/methodology/approach – The SJP‐WLCSP makes use of a delaminating layer to reduce the problem of CTE mismatch. In the SJP‐WLCSP, a delaminating layer is interposed between the top layer of the chip and the bottom insulating layer of the redistribution copper metal traces. As a result, the stress on the solder joints can be released by allowing cracks to form in the delaminating layer.Findings – To elucidate the thermo‐mechanical behaviour of tin‐lead eutectic solder joints and copper traces, a non‐linear analysis, based on a 3D finite el...

Sensitivity Design of DL-WLCSP Using DOE With Factorial Analysis Technology

Newer, faster, and smaller electronic packaging approaches with high I/O counts and more complex semiconductor devices are emerging steadily and rapidly. Wafer-level chip scaling package (WLCSP) has a high potential for future electronic packaging. However, the solder joint reliability for a large chip size of about 100 mm2 without underfill remains a troubling issue that urgently requires a solution. To this end, a double-layer WLCSP (DL-WLCSP) with stress compliant layers and dummy solder joint is adopted in this research in order to study the design parameters of enhancing the solder joint fatigue life. To ensure the validity of the analysis methodology, a test vehicle of Rambus DRAM is implemented to demonstrate the applicability and reliability of the proposed DL-WLCSP. The results of the thermal cycling in the experimental test show good agreement with the simulated analysis. Furthermore, to investigate the reliability impact of the design parameters, including solder volume, the arrangement of the die-side and substrate-side pad diameter, second compliant layer thickness, die thickness, and the printed circuit board (PCB) thickness, a design of experiment (DOE) with factorial analysis is adopted to obtain the sensitivity information of each parameter by the three-dimensional nonlinear finite-element models (FEMs). The statistics results of the analysis of variance reveal that the thickness of the second stress compliant layer and the volume of the solder joint can effectively reduce the stress concentration phenomenon, which occurs around the outer corner of the solder joint. In addition, the evident interaction between design parameters can also be obtained. The smaller thermal strains can be achieved through a better combination of design parameters of the geometry so as to provide the actual requirement of the physical information prior to manufacturing

The development of enhanced wafer level packaging

In this paper, one of the wafer level chip scale packaging (WL-CSP) patents issued by ERSO/ITRI, the double elastomer wafer level package, is implemented on the test vehicle of Rambus DRAM to demonstrate the applicability and reliability of WL-CSP for high performance devices. In this design, both thermal and electrical performance enhancements are considered. To demonstrate the reliability of the enhanced WL-CSP, both the component- and board-level criteria are studied, which includes the evaluation of UBM (under bump metallurgy) by adopting low cost electroless and electroplating Ni/Au processes. Results show that the developed thermally and electrically enhanced WL-CSP can pass the reliability tests of pre-con, TC (temperature cycling), PCT (pressure cooker test), and HST (humidity storage test) at component-level and PCT at board-level. Although the board-level TC is on-going, which targets 1000 cycles, early studies of typical FMA are presented here. Moreover, preliminary studies of improving the board-level TC reliability are also included in the paper.

3D Chip-to-Chip Stacking with Through Silicon Interconnects

The paper describes the newly development technology of 3D stacking packaging by introducing laser-drilled through silicon interconnect (LTSI). Compared to the recently abundant researches of 3D chip-to-wafer or wafer-to-wafer stacking, it demonstrated a more reliable and practical process flow to achieve the 3D stacking technology. The investigation of thermal effect and electrical properties on LTSI confirm that this newly low-cost interconnect technology could be a good candidate for both wafer stacking application and 3D SiP module.

Flexible Electronic-Optical Local Bus Modules to the Board-to-Board, Board-to-Chip, and Chip-to-Chip Optical Interconnection

In this paper, a flexible active E/O local bus module using multi-mode optical transmission is proposed to perform board-to-board, chip-to-chip, or board-to-chip optical interconnection with compatibility to traditionally electrical interfaces. In this proposed scheme, high speed modules or chips on tradition printed circuit board (PCB) can be directly interconnected through a flexible active E/O cable which can actively convert high speed signals to/from optical forms and then transmit optical signals through the optical waveguide layer. A 17-cm long prototyping of the proposed E/O local bus module is developed here to demonstrate the feasibility of short reach optical interconnection in board level applications

A Novel Design Structure for WLCSP With High Reliability, Low Cost, and Ease of Fabrication

Wafer level chip scale packaging (WLCSP) has some advantages, such as real die size packaging, high electrical performance, and low manufacturing cost. However, because the mechanical reliability of a large die can not be guaranteed due to the coefficient of thermal expansion (CTE) mismatch between silicon and organic printed circuit board (PCB), WLCSP technology is still not fully accepted. We have developed a new solder joint protection-WLCSP (SJP-WLCSP) structure with a delamination layer interposed between the top layer of the chip and the bottom insulating layer of the metal redistribution traces. The stress on the solder joints can be released by the cracks forming in the delamination layer, which protects the solder joints from cracking. Since the cracking of the delamination layer is irrelevant to the electrical circuits of the packaging, the packaged integrated circuits (IC) device remains functional. One of the possibilities for processing the SJP-WLCSP was implemented and validated successfully in the SiLK-wafer samples. The board level packaging samples, using the daisy chain resistance measurement passed 1000 cycles of the temperature cycling testing.

Design of double layer WLCSP using DOE with factorial analysis technology

Newer, faster and smaller electronic packaging approaches with high I/O counts and more complex semiconductor devices are emerging steadily and rapidly. Wafer level chip scaling package (WLCSP) has a high potential for future electronic packaging. However, the solder joint reliability for a large chip size of about 100 mm/sup 2/ without underfill is remains a troubling issue that urgently requires a solution. To this end, a double-layer WLCSP (DL-WLCSP) with stress compliant layer and dummy solder joint is proposed in this research in order to enhance the solder joint fatigue life. To ensure the validity of the analysis methodology, a test vehicle of Rambus DRAM is implemented to demonstrate the applicability and reliability of the proposed DL-WLCSP. The results of the thermal cycling in the experimental test show good agreement with the simulated analysis. Furthermore, to investigate the reliability impact of the design parameters, including solder volume, the arrangement of the die-side and substrate-side pad diameter, pitch, compliant layer thickness, die thickness, and the printed circuit board (PCB) thickness, a design of experiment (DOE) with factorial analysis is adopted to obtain the sensitivity information of each parameter by the three-dimensional nonlinear finite element models (FEM). The statistics results of the analysis of variance reveal that the thickness of the stress compliant layer and the volume of the solder joint can effectively reduce the stress concentration phenomenon, which occurs around the outer-corner of the solder joint. In addition, the evident interaction between design parameters can also be obtained. The smaller thermal strains can be achieved through a better combination of design parameters of the geometry so as to provide the actual requirement of the physical information prior to manufacturing.