Fulvio Mancarella

Carbon-Cap for Ohmic Contacts on Ion-Implanted 4H – SiC

A pyrolyzed photoresist film is commonly used as a protective cap of the surface of ion-implanted 4H-SiC wafers during the postimplantation annealing process with the aim to prevent Si sublimation and step bunching formation. Such a film that is called carbon-cap (C-cap) is always removed after postimplantation annealing and before any other processing step of the SiC wafer. Here, we show that this C-cap is a continuous, hard, black, mirrorlike, and planar thin film that can be patterned by a reactive ion etching O 2 -based plasma for the fabrication of ohmic contact pads on both Al + - and P + -implanted 4H-SiC. This C-cap material has an electrical resistivity of 1.5 × 10 -3 Ω cm and a good resistance against scratch. Al (1% Si) wires can be ultrasonically bonded on the C-cap pads. Such a bonding and the C-cap adhesion to the implanted 4H-SiC surface are stable for electrical characterizations in vacuum between room temperature and 450°C. The measured specific contact resistance of the C-cap on a 1 × 10 20 cm -3 p+-implanted 4H-SiC is 9 × 10- 5 Ω cm 2 at room temperature. Micro-Raman characterizations show that this C-cap is formed of a nanocrystalline graphitic phase.

Strain relaxation of GaAs/Ge crystals on patterned Si substrates

We report on the mask-less integration of GaAs crystals several microns in size on patterned Si substrates by metal organic vapor phase epitaxy. The lattice parameter mismatch is bridged by first growing 2-μm-tall intermediate Ge mesas on 8-μm-tall Si pillars by low-energy plasma enhanced chemical vapor deposition. We investigate the morphological evolution of the GaAs crystals towards full pyramids exhibiting energetically stable {111} facets with decreasing Si pillar size. The release of the strain induced by the mismatch of thermal expansion coefficients in the GaAs crystals has been studied by X-ray diffraction and photoluminescence measurements. The strain release mechanism is discussed within the framework of linear elasticity theory by Finite Element Method simulations, based on realistic geometries extracted from scanning electron microscopy images.

Material Properties Measurement and Numerical Simulation for Characterization of Ultra-Low-Power Consumption Hotplates

The results of a thorough thermoelectric characterization, performed both in a vacuum chamber and at atmospheric pressure, of ultra-low-power hotplates based on suspended structures with different layouts are presented in this work and compared with thermoelectric 2D and thermal 3D finite elements simulations. Electrical and thermal properties of the thin films used in the devices have been also measured, involving appropriate on-chip test structures, and their values were employed in both 2D and 3D model. Temperature vs. heating power experimental curves showed the great influence of conduction through air on power consumption and an excellent agreement with the simulated results.

Fabrication of fiber-optic broadband ultrasound emitters by micro-opto-mechanical technology

A micro-opto-mechanical system (MOMS) technology for the fabrication of fiber-optic optoacoustic emitters is presented. The described devices are based on the thermoelastic generation of ultrasonic waves from patterned carbon films obtained by the controlled pyrolysis of photoresist layers and fabricated on miniaturized single-crystal silicon frames used to mount the emitters on the tip of an optical fiber. Thanks to the micromachining process adopted, high miniaturization levels are reached in the fabrication of the emitters, and self-standing devices on optical fiber with diameter around 350 µm are demonstrated, potentially suited to minimally invasive medical applications. The functional testing of fiber-optic emitter prototypes in water performed by using a 1064 nm Q-switched Nd-YAG excitation laser source is also presented, yielding broadband emission spectra extended from low frequencies up to more than 40 MHz, and focused emission fields with a maximum peak-to-peak pressure level of about 1.2 MPa at a distance of 1 mm from the devices.

Influence of Grain Size on the Thermoelectric Properties of Polycrystalline Silicon Nanowires

The thermoelectric properties of doped polycrystalline silicon nanowires have been investigated using doping techniques that impact grain growth in different ways during the doping process. In particular, As- and P-doped nanowires were fabricated using a process flow which enables the manufacturing of surface micromachined nanowires contacted by Al/Si pads in a four-terminal configuration for thermal conductivity measurement. Also, dedicated structures for the measurement of the Seebeck coefficient and electrical resistivity were prepared. In this way, the thermoelectric figure of merit of the nanowires could be evaluated. The As-doped nanowires were heavily doped by thermal doping from spin-on-dopant sources, whereas predeposition from POCl3 was utilized for the P-doped nanowires. The thermal conductivity measured on the nanowires appeared to depend on the doping type. The P-doped nanowires showed, for comparable cross-sections, higher thermal conductivity values than As-doped nanowires, most probably because of their finer grain texture, resulting from the inhibition effect that such doping elements have on grain growth during high-temperature annealing.

Fabrication and testing of a high resolution extensometer based on resonant MEMS strain sensors

A novel type of linear extensometer with exceptionally high resolution of 4 nm based on MEMS resonant strain sensors bonded on steel and operating in a vacuum package is presented. The tool is implemented by means of a steel thin bar that can be pre-stressed in tension within two fixing anchors. The extension of the bar is detected by using two vacuum-packaged resonant MEMS double- ended tuning fork (DETF) sensors bonded on the bar with epoxy glue, one of which is utilized for temperature compensation. Both sensors are driven by a closed loop self-oscillating transresistance amplifier feedback scheme implemented on a PCB (Printed Circuit Board). On the same board, a microcontroller-based frequency measurement circuit is also implemented, which is able to count the square wave fronts of the MEMS oscillator output with a resolution of 20 nsec. The system provides a frequency noise of 0.2 Hz corresponding to an extension resolution of 4 nm for the extensometer. Nearly perfect temperature compensation of the frequency output is achieved in the temperature range 20–35 °C using the reference sensor.

Fabrication of DETF sensors in SOI technology with submicron air gaps using a maskless line narrowing technique

We report about the fabrication of double-ended tuning fork (DETF) single-crystal silicon sensors starting from SOI substrates in which a novel line narrowing technique is adopted in order to shrink the electrostatic coupling gaps between the moving and fixed electrodes. By using conventional near-UV lithography, this solution provides the possibility to control gaps scaled down to 200 nm on an oxide hard mask realized on the structural silicon layer, yielding air gaps with minimum feature size between 400 and 600 nm after the subsequent silicon deep reactive ion etching (DRIE) step. With the proposed process, DETF structures with length varying between 100 and 500 mum have been realized, with a process yield around 85% on a 4-inch SOI substrate. DC testing of the realized prototypes, performed in a SEM-based setup, and vacuum AC testing are also presented, providing a first evaluation of the device pull-in voltage, resonance frequency and Q factor.

Stacking Fault Analysis of Epitaxial 3C-SiC on Si(001) Ridges

The stacking faults (SFs) in 3C-SiC epitaxially grown on ridges deeply etched into Si (001) substrates offcut towards [110] were quantitatively analyzed by electron microscopy and X-ray diffraction. A significant reduction of SF density with respect to planar material was observed for the {111} planes parallel to the ridges. The highest SF density was found in the (-1-11) plane. A previously observed defect was identified as twins by electron backscatter diffraction.

Defect Reduction in Epitaxial 3C-SiC on Si(001) and Si(111) by Deep Substrate Patterning

The heteroepitaxial growth of 3C-SiC on Si (001) and Si (111) substrates deeply patterned at a micron scale by low-pressure chemical vapor deposition is shown to lead to space-filling isolated structures resulting from a mechanism of self-limitation of lateral expansion. Stacking fault densities and wafer bowing may be drastically reduced for optimized pattern geometries.

β-SiC NWs Grown on Patterned and MEMS Silicon Substrates

Cubic silicon carbide nanowires (-SiC or 3C-SiC NW) have been grown by Vapour Phase Epitaxy on (001) silicon substrates patterned by conventional photolithography and on Micro Electro Mechanical Systems (MEMS, e.g. cantilevers, springs, bridges) fabricated on (001) Silicon On Insulator (SOI) wafers. The NW morphology was investigated by scanning electron microscopy, showing that the nanowires grew selectively where a nickel thin layer was previously deposited, thanks to its catalytic action. High resolution transmission electron microscopy studies showed that the NWs are predominantly 3C polytype with <111> growth axis and stacking defects on (111) planes.