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Featured researches published by Fumiaki Endo.


electronic components and technology conference | 2011

Micro texture dependence of the mechanical and electrical reliability of electroplated copper thin film interconnections

Naokazu Murata; Naoki Saito; Fumiaki Endo; Ken Suzuki; Hideo Miura

Both mechanical and electronic properties of electroplated copper films used for interconnections were investigated experimentally considering the change of their micro texture caused by heat treatment. Since those properties varied drastically depending on the electroplating conditions and thermal history after the electroplating, a novel evaluation method of the crystallinity of grains and grain boundaries of the electroplated copper thin films has been proposed by applying the conventional electron back scatter diffraction method. It was found the porous grain boundaries in the films cause brittle mechanical and electrical fractures of the films. The proposed method was effective for evaluating the crystallinity of grain boundaries quantitatively, and thus, estimating both the mechanical and electrical properties of the films used for mass production.


Journal of Electronic Packaging | 2012

Minimization of the Local Residual Stress in 3D Flip Chip Structures by Optimizing the Mechanical Properties of Electroplated Materials and the Alignment Structure of TSVs and Fine Bumps

Kota Nakahira; Hironori Tago; Fumiaki Endo; Ken Suzuki; Hideo Miura

Since the thickness of stacked silicon chips in 3D integration has been thinned to less than 100 μm, the local thermal deformation of the chips has increased drastically because of the decrease of the flexural rigidity of the thinned chips. The clear periodic thermal deformation and thus, the local distribution of thermal residual stress appears in the stacked chips due to the periodic alignment of metallic bumps, and they sometimes deteriorate mechanical and electrical reliability of electronic products. In this paper, the dominant structural factors of the local residual stress in a silicon chip are investigated quantitatively based on the results of a three-dimensional finite element analysis and the measurement of the local residual stress in a chip using stress sensor chips. The piezoresistive strain gauges were embedded in the sensor chips. The length of each gauge was 2 μm, and an unit cell consisted of four gauges with different crystallographic directions. This alignment of the strain gauges enables us to measure the tensor component of three-dimensional stress fields separately. Test flip chip substrates were made of silicon chip on which the area-arrayed tin/copper bumps were electroplated. The width of a bump was fixed at 200 μm, and the bump pitch was varied from 400 μm to 1000 μm. The thickness of the copper bump was about 40 μm and that of tin layer was about 10 μm. This tin layer was used for the formation of rigid joint by alloying it with copper interconnection formed on a stress sensing chip. The measured amplitude of the residual stress increased from about 30 MPa to 250 MPa depending on the combination of materials such as bump, underfill, and interconnections. It was confirmed that both the material constant of underfill and the alignment structure of fine bumps are the dominant factors of the local deformation and stress of a silicon chip mounted on area-arrayed metallic bumps. It was also confirmed that not only the control of mechanical properties of electroplated copper thin films, but also the hound’s-tooth alignment of a through silicon via and a bump are indispensable for minimizing the packaging-induced stress in the three-dimensionally mounted chips. This test chip is very effective for evaluating the packaging-process-induced stress in 3D stacked chips quantitatively.


ieee international d systems integration conference | 2012

Minimization of the local residual stress in 3DICs by controlling the structures and mechanical properties of 3D interconnections

Kota Nakahira; Fumiaki Endo; Ryosuke Furuya; Ken Suzuki; Hideo Miura

Since the residual stress in a silicon chip mounted in 3D modules causes the degradation of both electrical and mechanical reliability, the dominant factors of the residual stress was investigated by using a finite element method and experiments applying 2-μm long piezoresistance strain gauges. The residual stress and local deformation of the chip were found to vary drastically depending on the mechanical properties of bumps and underfill and bump alignment structures.


Volume 9: Micro- and Nano-Systems Engineering and Packaging, Parts A and B | 2012

Micro-Texture Dependence of the Strength of Fine Metallic Bumps Used for Electronic Packaging

Fumiaki Endo; Naokazu Murata; Ken Suzuki; Hideo Miura

Electroplated copper bumps expected as fine metallic bumps for electronic packaging were investigated experimentally considering the change of micro texture dependence of their electroplating conditions and heat treatment after the electroplating. Not only Young’s modulus but also the strength of electroplated copper thin films changed drastically depending on the change of their micro texture, and these values were significantly different from conventional bulk copper. In addition, the strong anisotropy of Young’s modulus was observed between that along their thickness direction, and that parallel to their plane direction.Copyright


ECTC | 2011

Micro Texture Dependence of the Mechanical and Electrical Reliability of Electroplated Copper Thin Film Interconnections

Naokazu Murata; Naoki Saito; Fumiaki Endo; Ken Suzuki; Hideo Miura


The Japan Society of Applied Physics | 2013

Micro-Texture Dependence of Mechanical Properties of Fine Metallic Bumps Used for Three-Dimensional Electronic Packaging

K. Suzuki; Ryosuke Furuya; Fumiaki Endo; Hideo Miura


The Proceedings of the Materials and Mechanics Conference | 2012

PS20 Micro-Texture Dependence of the Strength of Fine Metallic Bumps Used for Electronic Packaging

Fumiaki Endo; Ken Suzuki; Hideo Miura


The Proceedings of Conference of Tohoku Branch | 2012

151 Micro-texture dependence of strength of fine metallic bumps used for electronic packaging

Fumiaki Endo; Ken Suzuki; Hideo Miura; Naokazu Murata


The Japan Society of Applied Physics | 2012

Dominant Structural Factors of Residual Stress Distribution in Stacked Silicon Chips Mounted in 3D Packages and Modules

K. Suzuki; Hironori Tago; Fumiaki Endo; Naokazu Murata; Hidekazu Miura


The Proceedings of the Materials and Mechanics Conference | 2011

OS2403 3D Semiconductor Assembly Structure with Low-Residual Stress Controlled by Mechanical Properties of Electroplated Cu Bumps

Fumiaki Endo; Kota Nakahira; Ken Suzuki; Hideo Miura

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