Ryosuke Furuya

Improvement of the reliability of TSV interconnections by controlling the crystallinity of electroplated copper thin films

The degradation process of the crystallinity of electroplated copper thin films, which are used for interconnections and micro bumps for 3D integration, during electromigration and stress-induced migration tests was observed clearly by applying an EBSD method. The grain boundary diffusion was the main reason for the degradation of the crystallographic quality in both grain boundaries and grains. The reliability of the interconnections was improved drastically by minimizing the lattice mismatch between the electroplated copper and its base material for electroplating. The large mismatch deteriorated the crystallographic quality of the electroplated copper thin films and thus, increased the shrinkage rate of the films caused by the annealing. The electronic resistivity of the crystallinity-controlled films decreases effectively, and their lives during electromigration test improved drastically. In addition, the residuals stress in the films annealed at 400°C decreased to the stress lower than their yielding stress, and therefore, no stress-induced migration was observed. These results clearly indicate that the control of the crystallinity of metallic interconnection is indispensable for assuring their long-life reliability.

Improvement of the crystallinity of electroplated copper thin films for highly reliable 3D interconnections

The degradation process of the crystallographic quality of copper thin films, which are used for interconnections and micro bumps for 3D integration, during electromigration and stress-induced migration tests is dominated by the diffusion along grain boundaries and the diffusion constant of copper varies drastically depending on the crystallinity of the films. The degradation process was visualized clearly by applying an electron back-scatter diffraction method. The copper atoms in the electroplated copper thin films migrated mainly in the area with low crystallinity, in other words, the area with high defect density. Since the crystallinity of the films was found to be dominated by the lattice mismatch between copper and the seed layer material used for electroplating, the integrity of the interface structure was improved by minimizing the lattice mismatch. It was validated that the introducing the thin layer with fine grains and random orientation is effective for minimizing the lattice mismatch and thus, improving the crystallographic quality of the electroplated copper thin-film interconnections.

Effect of the Lattice Mismatch Between Copper Thin-Film Interconnection and Base Material on the Crystallinity of the Interconnection

In the present study, a new material, ruthenium whose lattice mismatch against copper is about 6%, was used as the seed layer of electroplated copper thin-film interconnections for semiconductor devices. The crystallinity of the copper thin-film interconnections was evaluated through an EBSD (Electron Back-scattered Diffraction) method and it is found that the crystallinity of them is improved drastically compared with those electroplated on the copper seed. The resistance and electro migration (EM) tolerance of the copper interconnections are also improved a lot compared with the interconnections electroplated on copper seed. Based on these results, a new guideline to design highly reliable electroplated copper thin-film interconnection has been established.© 2013 ASME

Improvement of the Reliability of Thin-Film Interconnections Based on the Control of the Crystallinity of the Thin Films

Electroplated copper thin films have started to be applied to not only interconnections in printed wiring boards, but also thin film interconnections and TSV (Through Silicon Via) in semiconductor devices because of its low electric resistivity and high thermal conductivity. Thus, the electrical reliability of the electroplated copper interconnections was discussed experimentally.The relationship between the electrical properties and crystallographic quality (crystallinity) of electroplated copper thin-film interconnections was investigated. The crystallinity of the grains and grain boundaries of the interconnections was evaluated on the basis of the image quality (IQ) value obtained by electron back-scatter diffraction (EBSD) analysis. The electrical properties of the interconnections vary significantly depending on their crystallinity. The crystallinity also changed drastically as functions of electroplating conditions and the annealing temperature after electroplating.Although the electro migration (EM) resistance of the annealed interconnection is improved, the stress-induced migration (SM) is activated by a high residual tensile stress after annealing caused by the strong constraint of the shrinkage of the film during recrystallization. To improve its electrical reliability without heat treatment after the electroplating, the effects of the seed layer under the interconnections on the crystallinity of the electroplated film was investigated. As a result, the crystallinity was improved by changing the seed layer from Cu to Ru. In addition, the decrease in current density during electroplating also improves the crystallinity. Therefore, both introducing the Ru seed layer in addition to decreasing the current density during electroplating is effective for developing highly reliable copper interconnections.Copyright

Improvement of Crystallographic Quality of Electroplated Copper Thin-Film Interconnections for Through-Silicon Vias

The relationship between the electrical properties and crystallographic quality (crystallinity) of electroplated copper thin-film interconnections was investigated. The crystallinity of the grains and grain boundaries of the interconnections was evaluated on the basis of the image quality (IQ) value obtained by electron back-scatter diffraction (EBSD) analysis. The electrical properties of the interconnections vary markedly depending on their crystallinity. The crystallinity also changed markedly as functions of electroplating conditions and the annealing temperature after electroplating. Although the electro migration (EM) resistance of the annealed interconnection was improved, stress-induced migration (SM) was activated by a high residual stress after annealing. To improve electrical reliability without heat treatment after electroplating, the effects of the seed layer under the interconnections on the crystallinity were investigated. As a result, the crystallinity was improved by changing the seed layer from Cu to Ru. In addition, the decrease in current density during electroplating also improved the crystallinity. Therefore, both introducing the Ru seed layer and decreasing the current density during electroplating are effective for developing highly reliable copper interconnections.

Minimization of the local residual stress in 3DICs by controlling the structures and mechanical properties of 3D interconnections

Since the residual stress in a silicon chip mounted in 3D modules causes the degradation of both electrical and mechanical reliability, the dominant factors of the residual stress was investigated by using a finite element method and experiments applying 2-μm long piezoresistance strain gauges. The residual stress and local deformation of the chip were found to vary drastically depending on the mechanical properties of bumps and underfill and bump alignment structures.

Micro-texture dependence of stress-induced migration of electroplated copper thin film interconnections used for 3D integration

Effect of the micro texture of electroplated copper thin film interconnections on stress-induced migration was investigated experimentally and theoretically. The micro texture of electroplated copper thin films changed drastically as a function of the annealing temperature after the electroplating. However, stress-induced migration was activated even though the thin film interconnection was kept at room temperature after annealing. As a result, voids and hillocks appeared on the thin film interconnection. This is because high residual stress was caused by shrinkage of the thin film interconnection due to the densification caused by recrystallization. Molecular dynamics simulations showed that the diffusivity of copper atoms along grain boundaries with low crystallinity was enhanced significantly by high tensile residual stress. Therefore, the grain boundary diffusion accelerated by tensile residual stress is the main reason for the formation of hillocks and voids in the thin film interconnection after annealing.

Evaluation of the Crystallographic Quality of Electroplated Copper Thin-Film Interconnection Embedded in a Si Substrate

Electroplated copper thin films have started to be applied to the interconnection material in TSV structures because of its low electric resistivity and high thermal conductivity. However, the electrical resistivity of the electroplated copper thin films surrounded by SiO2 was found to vary drastically comparing with those of the conventional bulk material. This was because that the electroplated copper thin films consisted of grains with low crystallinity and grain boundaries with high defect density. Thus, in this study, both the crystallinity and electrical properties of the electroplated copper thin films embedded in the TSV structure was evaluated quantitatively by changing the electroplating conditions and thermal history after the electroplating. It was observed that many voids and hillocks appeared in the TSV structures after the high temperature annealing which was introduced for improving the crystallinity of the electroplated films. Therefore, it is very important to evaluate the crystallographic quality of the electroplated copper thin films after electroplating to assure both the mechanical and electrical properties of the films.Copyright

Evaluation of the crystallographic quality of electroplated copper thin-film interconnections embedded in TSV structures

Electroplated copper thin films have started to be applied to the Through Silicon Via (TSV) interconnections. Unfortunately, however, the electrical resistivity of the electroplated copper thin films was found to vary drastically comparing with those of the conventional bulk copper. This was because that the films consisted of grains with low crystallographic quality and a lot of porous grain boundaries. In this study, the electroplated copper thin film interconnections were embedded in a silicon substrate to model the TSV structure. It was observed that many voids and hillocks appeared on the surface of the films after annealed at 400°C. In addition, it was also found that the electrical resistivity of the films without annealing was much higher than that of bulk copper. As a result, it is very important to evaluate the crystallographic quality of the electroplated copper thin films after electroplated to assure the long-term reliability.