Fumihiko Hayashi

16 Mbit SRAM cell technologies for 2.0 V operation

Novel memory cell technologies for 2.0-V cell operation of 16-Mb SRAMs (static RAMs) have been developed. These technologies have realized 7.2- mu m/sup 2/ cell size, 4.4 effective cell ratio for high noise immunity, and 10/sup 13/-A/cell leakage current. The key features of these technologies include: (1) a symmetrical cell configuration; (2) an access transistor with an N/sup -/ offset resistor; (3) a ground plate expanded on the cell area; and (4) a poly Si TFT (thin film transistor) with an LDO (lightly doped offset) structure, all of which are based on a 0.4- mu m design rule using a SAC (self aligned contact) process. The access transistor with an N/sup -/ offset resistor increases the cell ratio without expanding cell size. The symmetrical cell configuration, the ground plate, and the TFT with the LDO structure contribute to cell operation stability.<<ETX>>

A 3.3-V 12-ns 16-Mb CMOS SRAM

The authors describe a 16 Mbit (2 M*8) SRAM with a 12-ns access time using a 0.4- mu m quadruple-polysilicon, double-metal CMOS technology with TFT (thin-film transistor) load memory cells. An access time of 12 ns is obtained with an optimized rotated memory cell array layout and a read bus midlevel voltage preset scheme (RBMIPS). An on-chip test circuit is included for efficient testing. The test circuit has three modes: redundant rows test, redundant columns test, and 16-bit parallel test. >

A highly stable SRAM memory cell with top-gated P-N drain poly-Si TFTs for 1.5 V operation

A novel memory cell has been proposed for low voltage operated, high speed and high density SRAMs. Features of this cell are (1) high performance poly-Si TFT loads utilizing bipolar action positively, and (2) a node contact structure which keeps current drivability of TFTs to the cell nodes high by the elimination of parasitic high resistance regions. The minimum operation voltage of 1.5 V has been confirmed by 0.3 /spl mu/m design rule 64 kbit SRAMs without a boosted word-line scheme.

A symmetric diagonal driver transistor SRAM cell with imbalance suppression technology for stable low voltage operation

A symmetric diagonal driver transistor (SDDT) cell has been developed for low voltage SRAM operation which exhibits high alignment tolerance. This new symmetric cell layout substantially suppresses the imbalance in a pair of cell transistor characteristics and, combined with silicon nitride self-aligned contact (Si/sub 3/N/sub 4/-SAC) and low resistance ground-line structures, results in a minimum operation voltage of 1.9 V, which is 0.3 V lower than that of the conventional split word line cell.

Characterizing subthreshold behavior in poly-Si TFTs based on interface trap states

The subthreshold behavior in poly-Si TFTs (Thin Film Transistors) has been analyzed in detail. It has been demonstrated that the high subthreshold slope factor and the back bias dependence of the subthreshold characteristics can be reproduced by the model based on Si-SiO/sub 2/ interface trap states. The importance of reducing the interface trap density in poly-Si TFTs is shown.<<ETX>>