Fumihiko Hayashi
NEC
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Featured researches published by Fumihiko Hayashi.
international electron devices meeting | 1991
Hiroaki Ohkubo; S. Horiba; Fumihiko Hayashi; T. Andoh; M. Kawaguchi; Y. Ochi; M. Soeda; H. Nozue; Hironobu Miyamoto; Masayoshi Ohkawa; Toshiyuki Shimizu; I. Sasaki
Novel memory cell technologies for 2.0-V cell operation of 16-Mb SRAMs (static RAMs) have been developed. These technologies have realized 7.2- mu m/sup 2/ cell size, 4.4 effective cell ratio for high noise immunity, and 10/sup 13/-A/cell leakage current. The key features of these technologies include: (1) a symmetrical cell configuration; (2) an access transistor with an N/sup -/ offset resistor; (3) a ground plate expanded on the cell area; and (4) a poly Si TFT (thin film transistor) with an LDO (lightly doped offset) structure, all of which are based on a 0.4- mu m design rule using a SAC (self aligned contact) process. The access transistor with an N/sup -/ offset resistor increases the cell ratio without expanding cell size. The symmetrical cell configuration, the ground plate, and the TFT with the LDO structure contribute to cell operation stability.<<ETX>>
international solid-state circuits conference | 1992
Hiroyuki Goto; Hiroaki Ohkubo; Kenji Kondou; Masayoshi Ohkawa; Hitoshi Mitani; S. Horiba; Masakazu Soeda; Fumihiko Hayashi; Yutaro Hachiya; Toshiyuki Shimizu; Manabu Ando; Zensuke Matsuda
The authors describe a 16 Mbit (2 M*8) SRAM with a 12-ns access time using a 0.4- mu m quadruple-polysilicon, double-metal CMOS technology with TFT (thin-film transistor) load memory cells. An access time of 12 ns is obtained with an optimized rotated memory cell array layout and a read bus midlevel voltage preset scheme (RBMIPS). An on-chip test circuit is included for efficient testing. The test circuit has three modes: redundant rows test, redundant columns test, and 16-bit parallel test. >
international electron devices meeting | 1996
Fumihiko Hayashi; Hiroaki Ohkubo; Toshifumi Takahashi; S. Horiba; Kenji Noda; Tetsuya Uchida; Toshiyuki Shimizu; Norikazu Sugawara; Shigetaka Kumashiro
A novel memory cell has been proposed for low voltage operated, high speed and high density SRAMs. Features of this cell are (1) high performance poly-Si TFT loads utilizing bipolar action positively, and (2) a node contact structure which keeps current drivability of TFTs to the cell nodes high by the elimination of parasitic high resistance regions. The minimum operation voltage of 1.5 V has been confirmed by 0.3 /spl mu/m design rule 64 kbit SRAMs without a boosted word-line scheme.
symposium on vlsi technology | 1996
S. Horiba; T. Takahashi; Hiroaki Ohkubo; Kenji Noda; Fumihiko Hayashi; T. Uchida; T. Yokoyama; Koichi Ando; T. Yoshida; Takasuke Hashimoto; Toshiyuki Shimizu
A symmetric diagonal driver transistor (SDDT) cell has been developed for low voltage SRAM operation which exhibits high alignment tolerance. This new symmetric cell layout substantially suppresses the imbalance in a pair of cell transistor characteristics and, combined with silicon nitride self-aligned contact (Si/sub 3/N/sub 4/-SAC) and low resistance ground-line structures, results in a minimum operation voltage of 1.9 V, which is 0.3 V lower than that of the conventional split word line cell.
international electron devices meeting | 1993
Fumihiko Hayashi; H. Ikeuchi; M. Kitakata; T. Sasaki
The subthreshold behavior in poly-Si TFTs (Thin Film Transistors) has been analyzed in detail. It has been demonstrated that the high subthreshold slope factor and the back bias dependence of the subthreshold characteristics can be reproduced by the model based on Si-SiO/sub 2/ interface trap states. The importance of reducing the interface trap density in poly-Si TFTs is shown.<<ETX>>
Archive | 1997
Fumihiko Hayashi
Archive | 1994
Fumihiko Hayashi
Archive | 1998
Fumihiko Hayashi
symposium on vlsi technology | 1991
Hiroshi Furuta; Fumihiko Hayashi; M. Ohkawa; Toshiyuki Shimizu; M. Ando; Y. Inoue; I. Sasaki
Archive | 1992
Masayoshi Ohkawa; Fumihiko Hayashi