Hiroaki Ohkubo

High sensitivity and no-cross-talk pixel technology for embedded CMOS image sensor

A high-photosensitivity and no-crosstalk pixel technology has been developed for an embedded active-pixel CMOS image sensor, by using a 0.35-/spl mu/m CMOS logic process. To increase the photosensitivity, we developed a deep p-well photodiode and an antireflective film, consisting of Si/sub 3/N/sub 4/ film, for the photodiode surface. To eliminate the high voltage required for the reset transistor in the pixel, we used a depletion-type transistor as the reset transistor. The reset transistor also operates as an overflow control gate, which enables antiblooming overflow when excess charge is generated in the photodiode by high-illumination conditions. To suppress pixel crosstalk caused by obliquely incident light, a double-metal photoshield was used, while crosstalk caused by electron diffusion in the substrate was suppressed by using the deep p-well photodiode. A 1/3-in 330-k-pixel active-pixel CMOS image sensor was fabricated using this technology. A sensitivity improvement of 110% for 550-nm incident light was obtained by using the deep p-well photodiode, while an improvement of 24% was obtained by using the antireflective film. The pixel crosstalk was suppressed to less than 1% throughout the range of visible light.

A signal-processing CMOS image sensor using a simple analog operation

A high-density CMOS image sensor has a normal mode and three signal-processing function modes: wide dynamic-range mode, motion-detection mode, and edge-extraction mode. Small pixel and real-time operation are achieved by using a four-transistor pixel scheme and column-parallel on-chip analog operation.

16 Mbit SRAM cell technologies for 2.0 V operation

Novel memory cell technologies for 2.0-V cell operation of 16-Mb SRAMs (static RAMs) have been developed. These technologies have realized 7.2- mu m/sup 2/ cell size, 4.4 effective cell ratio for high noise immunity, and 10/sup 13/-A/cell leakage current. The key features of these technologies include: (1) a symmetrical cell configuration; (2) an access transistor with an N/sup -/ offset resistor; (3) a ground plate expanded on the cell area; and (4) a poly Si TFT (thin film transistor) with an LDO (lightly doped offset) structure, all of which are based on a 0.4- mu m design rule using a SAC (self aligned contact) process. The access transistor with an N/sup -/ offset resistor increases the cell ratio without expanding cell size. The symmetrical cell configuration, the ground plate, and the TFT with the LDO structure contribute to cell operation stability.<<ETX>>

A 500 MHz 4 Mb CMOS pipeline-burst cache SRAM with point-to-point noise reduction coding I/O

A secondary cache SRAM is an indispensable CPU partner in a high-performance system. The main objectives are: 1) pipeline burst operation; 2) 32b 500MHz (2GB/s) I/Os, and 3) point-to-point communication with a CPU, as well as shortened latency and reduced noise and power caused by high-speed, high-bandwidth I/O operation. A pre-fetched pipeline scheme enables the cycle time for an internal memory core (I-cycle) to be extended by N times that of an external bus cycle (E-cycle). This is modified to an SRAM to achieve both 4b pipeline-burst cache operation and 500MHz I/O frequency. In this case, I-cycle time of 8ns is four times E-cycle time (2ns).

A 3.3-V 12-ns 16-Mb CMOS SRAM

The authors describe a 16 Mbit (2 M*8) SRAM with a 12-ns access time using a 0.4- mu m quadruple-polysilicon, double-metal CMOS technology with TFT (thin-film transistor) load memory cells. An access time of 12 ns is obtained with an optimized rotated memory cell array layout and a read bus midlevel voltage preset scheme (RBMIPS). An on-chip test circuit is included for efficient testing. The test circuit has three modes: redundant rows test, redundant columns test, and 16-bit parallel test. >

A highly stable SRAM memory cell with top-gated P-N drain poly-Si TFTs for 1.5 V operation

A novel memory cell has been proposed for low voltage operated, high speed and high density SRAMs. Features of this cell are (1) high performance poly-Si TFT loads utilizing bipolar action positively, and (2) a node contact structure which keeps current drivability of TFTs to the cell nodes high by the elimination of parasitic high resistance regions. The minimum operation voltage of 1.5 V has been confirmed by 0.3 /spl mu/m design rule 64 kbit SRAMs without a boosted word-line scheme.

A symmetric diagonal driver transistor SRAM cell with imbalance suppression technology for stable low voltage operation

A symmetric diagonal driver transistor (SDDT) cell has been developed for low voltage SRAM operation which exhibits high alignment tolerance. This new symmetric cell layout substantially suppresses the imbalance in a pair of cell transistor characteristics and, combined with silicon nitride self-aligned contact (Si/sub 3/N/sub 4/-SAC) and low resistance ground-line structures, results in a minimum operation voltage of 1.9 V, which is 0.3 V lower than that of the conventional split word line cell.