Fumiki Aiso

Depletion-type Cell-Transistor of 23 nm Cell Size on Partial SOI Substrate for NAND Flash Memory

1. Abstract To reduce the short channel effect for memory cell transistors beyond 2Xnm cell size for NAND Flash memories, we propose a depletion-type cell transistor fabricated on a self-manufactured partial SOI substrate by conventional LSI process and solid phase epitaxy. The memory cell transistors with stack-gate show well program / erase properties and have the typical S-factor of 366mV/decay. Short channel effect is reduced substantially to available level for 2Xnm size NAND Flash memory.

Engineering of Si-rich Nitride Charge-Trapping Layer for Highly Reliable MONOS Type NAND Flash Memory with MLC Operation

The relationship between chemical structure (N/Si ratio) or physical structure (laminate structure) of Si-rich nitride charge-trapping layer for MONOS and its electrical characteristics (Program/Erase window, fresh data retention and data retention after Program/Erase cycling stress) are investigated in detail. A laminate structure of Si-rich nitride has been developed that can realize a sufficient Program/Erase window and excellent data retention for MLC operation.

Engineering of Si-Rich Nitride Charge-Trapping Layer for Highly Reliable Metal–Oxide–Nitride–Oxide–Semiconductor Type NAND Flash Memory with Multi-Level Cell Operation

The relationship between chemical structure (N/Si ratio) or physical structure (bilayer or laminate structure) of Si-rich nitride charge-trapping layer for metal–oxide–nitride–oxide–semiconductor (MONOS) type NAND flash memory and its electrical characteristics (including program/erase Vth window, fresh cell data retention and data retention after program/erase cycling stress) are investigated in detail. A bilayer charge-trapping structure formed by two different composite Si-rich nitride films has been developed that can realize a sufficient program/erase window and excellent data retention characteristics for multi-level cell (MLC) operation.

Depletion-Type Cell-Transistor on Partial Silicon-on-Insulator Substrate for 2× nm Generation Floating-Gate NAND Electrically Erasable Programmable Read Only Memory

To reduce the short-channel effect for memory cell transistors beyond 2× nm cell size for NAND electrically erasable programmable read only memories (EEPROMs), we propose a depletion-type cell transistor fabricated on a self-manufactured partial silicon-on-insulator (SOI) substrate by conventional LSI process and solid-phase epitaxy. The memory cell transistors with stack-gate show good program/erase properties and have the good S-factor of 309 mV/decade, wide enough threshold voltage (Vth) window of 15 V between program and erase state, and fast enough program and erase time of 100 µs and 100 µs. And we observed no significant Vth-window narrowing and increase in Vth of about 1 V after 1000 cycling test. Operation bias sets of the depletion-type NAND EEPROM are as same as the sets of conventional NAND EEPROM and no peripheral circuit design change is needed. The short-channel effect is reduced substantially to available level for 2× nm size NAND EEPROM.