Ichiro Mizushima

Fabrication of Silicon-on-Nothing Structure by Substrate Engineering Using the Empty-Space-in-Silicon Formation Technique

A practical method for the fabrication of a silicon on nothing (SON) structure with the desired size and shape has been developed by using the empty-space-in-silicon (ESS) formation technique. It was found that the SON structure could be precisely controlled by the initial shape and layout of the trenches. The size of ESS is determined by the size of the initial trench. The desired shapes of ESS, such as spherical, pipe-shaped and plate-shaped, can be fabricated by changing the arrangement of the initial trenches. The fabricated SON region over ESS has excellent crystallinity adoptable for ultra-large-scale integrated circuit (ULSI) applications. The SON structure would be a promising substrate structure for various manufacturing technologies, such as the micro-electro-mechanical system (MEMS), photonic crystals and waveguides.

Micro-structure Transformation of Silicon: A Newly Developed Transformation Technology for Patterning Silicon Surfaces using the Surface Migration of Silicon Atoms by Hydrogen Annealing

The micro-structure transformation of silicon (MSTS), which is a transformation technology for patterning silicon surfaces by hydrogen annealing, is presented for the first time. The transformation was controlled by the parameters of annealing pressure as well as annealing time and temperature. Voids of sub-micrometer regime size can be intentionally formed in the silicon substrates by making use of transformation. Electrical characteristics, such as the reliability of the thin dielectrics formed in the deep trenches, were improved with the aid of the MSTS process, due to the flattening of the inside surface of the trenches and the rounding of the corners. The mechanism of the transformation by MSTS was studied by means of molecular dynamics, which clearly shows the migration of silicon atoms on the surface. MSTS is a promising technology for the fabrication of future integrated circuits in silicon.

Trench transformation technology using hydrogen annealing for realizing highly reliable device structure with thin dielectric films

The shape and the surface morphology of the trench structure was successfully transformed by the annealing in hydrogen ambient. The corner was rounded and the surface morphology was smoothened on the inside of the trench. Electrical characteristics of the thin oxide grown in the deep trench capacitor were drastically improved. The hydrogen annealing condition was optimized based on the transformation mechanism.

Hole Generation without Annealing in High Dose Boron Implanted Silicon: Heavy Doping by B12 Icosahedron as a Double Acceptor

A high hole concentration region of about 1×1021 cm-3 was generated without any post-annealing by the implantation of high doses of boron into silicon substrates. X-ray photoelectron spectroscopy (XPS) measurement and Fourier transform IR spectroscopy (FTIR) absorption spectra revealed that B12 icosahedra were created in as-implanted samples. A new model of the generation of holes is proposed in which B12 icosahedron acts as a double acceptor.

Facet-Free Si Selective Epitaxial Growth Adaptable to Elevated Source/Drain MOSFETs with Narrow Shallow Trench Isolation

A novel selective epitaxial growth (SEG) process that realizes a facet-free elevated source/drain (S/D) is proposed. The key points are the appropriate selection of the gate-sidewall material and its structural improvement. It was observed that the facet was not formed adjacent to SiN in contrast to the SiO2 case. Therefore, SiN is selected as a gate-sidewall. The novel gate-sidewall is constructed from a SiN sidewall and SiO2 liner layer which acts as a sidewall reactive ion etching (RIE) stopper. The SiO2 liner layer is lateral etched by wet treatment. By the SEG process, the facet, which is formed adjacent to the SiO2 liner is screened out within the lateral etched region, and no facet is observed along the SiN sidewall. Si lateral overgrowth on the shallow trench isolation (STI) region was also confirmed to be controllable in the facet-free SEG process. This novel SEG process was found to be successfully adapted to facet-free elevated S/D.

Conduction mechanism of high‐resistivity polycrystalline silicon films

The electrical properties of polycrystalline silicon films deposited by low‐pressure chemical vapor deposition and doped by boron, phosphorus, or arsenic with ion implantation, are investigated, and it is found that the resistivity versus donor concentration curve has a peak point for the completely depleted samples. An improved conduction model for the high‐resistivity polycrystalline silicon films is proposed. The theoretical results are in reasonable agreement with experiment. It is shown that the trap level located at the grain boundary exists at 0.51 eV above the valence‐band edge and that the hole current dominates the whole current through the films for all of the lightly doped samples, even for the donor‐doped samples.

Precipitation of Boron in Highly Boron-Doped Silicon

The clustering of boron in highly boron-doped silicon and its influence on electrical deactivation are reported. Highly boron-doped crystalline silicon was fabricated as a starting material by solid phase epitaxy of boron-doped amorphous silicon films. Boron can be supersaturated in the crystallized samples annealed at a low temperature of about 600°C. A lot of precipitates, containing clustered boron, were observed in the samples annealed at high temperatures of about 1000°C. The chemical states and the atomic configuration of boron in samples annealed at various temperatures corresponded to the electrical deactivation of boron.

SOI/Bulk Hybrid Wafer Fabrication Process Using Selective Epitaxial Growth (SEG) Technique for High-End SoC Applications

The size of SiN region and the growth condition were investigated for the robust process of selective epitaxial growth for the fabrication of the silicon on insulator (SOI)/bulk hybrid wafer. Silicon nucleation on SiN layer was observed during the selective epitaxial growth process using SiH2Cl2/HCl/H2 mixture at 1000–1100°C. At the center of SiN region, the coverage of SiN region by nucleated silicon increases with the increase of growth rate of epitaxial silicon layer, deposition time and the size of SiN region. At the edge of SiN region, there are nucleation-free regions. Also, silicon nucleation on SiN layer has an incubation time. The incubation time increases with the decrease of the size of SiN region. The incubation time for SiN region which has rectangular shape is longer than that for SiN region of square shape which has the same area. Under the condition which has the same growth rate regardless of the deposition temperature, there is an optimum temperature for suppression of silicon nucleation on SiN layer. These facts mean that the size of the SiN cap layer of SOI region should be decided carefully for the fabrication of SOI/bulk hybrid wafer by the selective epitaxial growth method.

Diffusion and Segregation of Carbon in SiO2 Films

Diffusion of carbon in SiO2 films and its segregation at the Si/SiO2 interface were investigated using carbon-incorporated borophosphosilicateglass (BPSG) films and carbon-implanted SiO2 films. It was found that carbon atoms diffuse in SiO2 film at a temperature as low as 500° C. Carbon atoms segregated at the Si/SiO2 interface and induced positive charge. The positive charge density was proportional to the segregated carbon concentration. Field emission transmission electron microscopy (FE-TEM) and electron energy loss spectra (EELS) observations revealed that carbon atoms exist on the SiO2 side of the interface, and another carbon-rich phase is formed in SiO2.

Carbon Incorporation into Substitutional Silicon Site by Molecular Carbon Ion Implantation and Recrystallization Annealing as Stress Technique in n-Metal–Oxide–Semiconductor Field-Effect Transistor

Since the lattice constant of silicon-carbon (Si:C) is smaller than that of Si, Si:C embedded in the source and drain (e-Si:C S/D) can induce tensile stress in the channel and improve the electron mobility of n-metal–oxide–semiconductor field-effect transistor (nMOSFETs). In this research, molecular carbon (C) ion implantation and recrystallization schemes employed to achieve strained Si:C films with a high substitutionally incorporated carbon concentration ([C]sub) and a high ratio of substitution were studied. Several recrystallization techniques including rapid-thermal-annealing (RTA)-based solid phase epitaxy (SPE), spike annealing, and nonmelt laser annealing have been used to optimize C incorporation into Si and strain application. Results of these different implantation and annealing techniques are compared and discussed. Furthermore, we proposed the first recrystallization by nonmelt laser annealing and the co-incorporation of a dopant that increases the rate of Si regrowth and has a covalent radius slightly different from that of Si. These processes markedly promoted the recrystallization of C densely incorporated in an amorphous Si layer and improved the crystallinity of strained Si:C films while maintaining a high [C]sub at a high ratio of substitution.