Fumio Arakawa

An embedded processor core for consumer appliances with 2.8GFLOPS and 36M polygons/s FPU

An embedded-processor core implemented in a 130nm CMOS process runs at 400MHz and achieves 720MIPS with a power of 250mW and 2.8GFLOPS. The processor employs a dual-issue seven-stage pipeline architecture while maintaining 1.8MIPS/MHz instruction efficiency of the previous five-stage processor. The processor is suitable for digital consumer appliances.

A resume-standby application processor for 3G cellular phones

A 389MIPS application processor for 3G cellular phones is implemented in a 0.13/spl mu/m dual-V, process. This dual-issue superscalar CPU with DSP runs at 216MHz at 1.2V and provides a resume-standby mode with a quick recovery feature using data retention of memory. The leakage current is estimated to be 98/spl mu/A when the power supply is internally cut off.

SH4 RISC multimedia microprocessor

Unique, floating-point length-4 vector instructions prove more effective than conventional SIMD architecture for 3D graphics processing.

The Gmicro/500 superscalar microprocessor with branch buffers

The Gmicro/500, which features a RISC-like dual-pipeline structure for high-speed execution of basic instructions and represents a significant advance for the TRON architecture, is presented. Upwardly-object-compatible with earlier members of the Gmicro series, this microprocessor uses resident dedicated branch buffers to greatly enhance branch instruction execution speed. Its microprograms simultaneously use dual execution blocks to execute high-level language instructions effectively. Fabricated with a 0.6- mu m CMOS technology on a 10.9-mm*16-mm die, the chip operates at 50/66 MHz and achieves a processing rate of 100/132 MIPS.<<ETX>>

SH-X: an embedded processor core for consumer appliances

A SuperH™ embedded processor core SH-X implemented in a 130-nm CMOS process running at 400 MHz achieved 720 MIPS and 2.8 GFLOPS at a power of 250 mW under worst-case conditions. It has a dual-issue seven-stage pipeline architecture, but reaches the 1.8 MIPS/MHz of the previous five-stage processor. The on-chip memory configuration is tuned for digital consumer appliances. A new resume-standby mode enables a standby current of less than 100, μA and a 3-ms recovery time. The processor meets the requirements of a wide range of applications, and is suitable for digital appliances aimed at the consumer market, such as cellular phones, digital still/video cameras, and car navigation systems.

Low-power design of 90-nm SuperH/spl trade/ processor core

A low-power SuperH/spl trade/ embedded processor core, the SH-X2, has been designed in 90-nm CMOS technology. The power consumption was reduced by using hierarchical fine-grained clock gating to reduce the power consumption of the flip-flops and clock-tree, synthesis and a layout that support implementation of the clock gating, and several-level power evaluations for RTL refinement. With this clock gating and RTL refinement, the power consumption of the clock-tree and flip-flops was reduced by 35% and 59%, including the process shrinking effects, respectively. As a result, the SH-X2 achieved 6,000 MIPS/W using a Renesas low-power process with lowered voltage. Its performance-power efficiency was 25% better than that of a 130-nm-process SH-X.

A 200 MHz 1.2 W 1.4 GFLOPS microprocessor with graphic operation unit

This 200 MHz CMOS 2-issue superscalar microprocessor is redesigned with a 0.25 /spl mu/m 5-metal-layers CMOS process (L/sub eff/=0.20 /spl mu/m). In this chip 3.2M transistors are implemented in a 7.6/spl times/7.6 mm/sup 2/ die. This chip for low-cost graphic, embedded applications achieves 1.4 GFLOPS at 200 MHz with low-power consumption. This chip integrates CPU, FPU, 8 kB direct-mapped instruction cache (IC), 16 kB direct-mapped data cache (DC), MMU (64-entry unified TLB and 4-entry ITLB), bus interface logic, and six peripherals which are DMAC, timer unit (TMU), real time clock (RTC), serial comm. interface (SCI), interrupt controller (INTC), and emulation/debug unit (EMU). The bus interface provides glueless connections to SRAM, DRAM, SDRAM, burst-ROM, and PCMCIA, bus operation includes 8-, 16-, 32-, and 64b bus widths.

Autonomous decentralized low-power system LSI using self-instructing predictive shutdown method

There is a strong demand from the mobile telecommunications industry for LSIs that achieve higher performance using less power. However, it is almost impossible in a short design period for a circuit designer to carry out an optimal design with both the power and performance items of a LSI having tens of millions of logic gates. Furthermore, a considerable component of the DC-leakage current originates from the subthreshold, gate leakage, and junction leakage currents of the MOS transistor even when the LSI is in an active state. This paper proposes an autonomous decentralized system LSI where each block has a predictive shutdown function using an MOS power switch controlled by a method based on self-instruction.

Design methodology for GMICRO/500 TRON microprocessor

Describes the design methodology used for the architecture of the GMICRO/500 TRON CISC superscalar microprocessor. Its minimum performance goal is 50 MHz, 100 VAX-MIPS at 5 V. This severe goal and the CISC superscalar architecture make the design time long and require a lot of manpower and computer resources. The C language and Unix environment are used to reduce the cost of the logic simulation. Synopsis and GDT are used to accelerate the logic design and the cell/macro design. A supercomputer is used to shorten the gate-level simulation time. The total design manpower is under 603 man-months.<<ETX>>

An embedded processor core for consumer appliances with 5.6 GFLOPS and 73M polygons/s FPU

An embedded-processor core implemented in a 130nm CMOS process runs at 400MHz and achieves 720MIPS with a power of 250mW and 2.8GFLOPS. The processor employs a dual-issue seven-stage pipeline architecture while maintaining 1.8MIPS/MHz instruction efficiency of the previous five-stage processor. The processor is suitable for digital consumer appliances.