Kunio Uchiyama

A 1000-MIPS/W microprocessor using speed adaptive threshold-voltage CMOS with forward bias

Substrate bias is continuously controlled from -1.5 V (backward bias) to 0.5 V (forward bias) to compensate for fabrication fluctuation, supply voltage variation, and operating temperature variation. A speed-adaptive threshold-voltage (SA-Vt) CMOS with forward bias is used in a 4.3M transistor microprocessor. The SA-Vt CMOS with forward bias occupies 320/spl times/400 /spl mu/m/sup 2/ and consumes 4 mA. The processor provides 400 VAX MIPS at 1.5 to 1.8 V with 320 to 380mW dissipation. It achieves >1000-MIPS/W performance.

An 18-/spl mu/A standby current 1.8-V, 200-MHz microprocessor with self-substrate-biased data-retention mode

A 1.8 V 200 MHz low-subthreshold-leakage-current microprocessor is fabricated in a 0.2 /spl mu/m CMOS technology. It uses a switched substrate-impedance scheme to bias substrates while maintaining 200 MHz operating speed. It also offers a battery backup capability in a self substrate-biased data retention mode, in which it consumes only 17.8 /spl mu/A operating off a 1.0 V supply.

An 8640 MIPS SoC with Independent Power-Off Control of 8 CPUs and 8 RAMs by An Automatic Parallelizing Compiler

Power efficient SoC design for embedded applications requires several independent power-domains where the power of unused blocks can be turned off. An SoC for mobile phones defines 23 hierarchical power domains but most of the power domains are assigned for peripheral IPs that mainly use low-leakage high-Vt transistors. Since high-performance multiprocessor SoCs use leaky low-Vt transistors for CPU sections, leakage power savings of these CPU sections is a primary objective. We develop an SoC with 8 processor cores and 8 user RAMs (1 per core) targeted for power-efficient high-performance embedded applications. We assign these 16 blocks to separate power domains so that they can be independently be powered off. A resume mode is also introduced where the power of the CPU is off and the user RAM is on for fast resume operation. An automatic parallelizing compiler schedules tasks for each CPU core and also performs power management for each CPU core. With the help of this compiler, each processor core can operate at a different frequency or even dynamically stop the clock to maintain processing performance while reducing average operating power consumption. The compiler also executes power-off control of unnecessary CPU cores.

SH4 RISC multimedia microprocessor

Unique, floating-point length-4 vector instructions prove more effective than conventional SIMD architecture for 3D graphics processing.

A 4320MIPS Four-Processor Core SMP/AMP with Individually Managed Clock Frequency for Low Power Consumption

A 4320MIPS four-core SoC that supports both SMP and AMP for embedded applications is designed in 90nm CMOS. Each processor-core can be operated with a different frequency dynamically including clock stop, while keeping data cache coherency, to maintain maximum processing performance and to reduce average operating power. The 97.6mm2 die achieves a floating-point performance of 16.8GFLOPS

A 45nm 37.3GOPS/W heterogeneous multi-core SoC

We develop a heterogeneous multi-core SoC for applications, such as digital TV systems with IP networks (IP-TV) including image recognition and database search. Figure 5.3.1 shows the chip features. This SoC is capable of decoding 1080i audio/video data using a part of SoC (one general-purpose CPU core, video processing unit called VPU5 and sound processing unit called SPU) [1]. Four dynamically reconfigurable processors called FE [2] are integrated and have a total theoretical performance of 41.5GOPS and power consumption of 0.76W. Two 1024-way matrix-processors called MX-2 [3] are integrated and have a total theoretical performance of 36.9GOPS and power consumption of 1.10W. Overall, the performance per watt of our SoC is 37.3GOPS/W at 1.15V, the highest among comparable processors [4–6] excluding special-purpose codecs. The operation granularity of the CPU, FE and MX-2 are 32bit, 16bit, and 4bit respectively, and thus we can assign the appropriate processor for each task in an effective manner. A heterogeneous multi-core approach is one of the most promising approaches to attain high performance with low frequency, or low power, for consumer electronics application and scientific applications, compared to homogeneous multi-core SoCs [4]. For example, for image-recognition application in the IP-TV system, the FEs are assigned to calculate optical flow operation [7] of VGA (640×480) size video data at 15fps, which requires 0.62GOPS. The MX-2s are used for face detection and calculation of the feature quantity of the VGA video data at 15fps, which requires 30.6GOPS. In addition, general-purpose CPU cores are used for database search using the results of the above operations, which requires further enhancement of CPU. The automatic parallelization compilers analyze parallelism of the data flow, generate coarse grain tasks, schedule tasks to minimize execution time considering data transfer overhead for general-purpose CPU and FE.

The Gmicro/500 superscalar microprocessor with branch buffers

The Gmicro/500, which features a RISC-like dual-pipeline structure for high-speed execution of basic instructions and represents a significant advance for the TRON architecture, is presented. Upwardly-object-compatible with earlier members of the Gmicro series, this microprocessor uses resident dedicated branch buffers to greatly enhance branch instruction execution speed. Its microprograms simultaneously use dual execution blocks to execute high-level language instructions effectively. Fabricated with a 0.6- mu m CMOS technology on a 10.9-mm*16-mm die, the chip operates at 50/66 MHz and achieves a processing rate of 100/132 MIPS.<<ETX>>

Functional verification of the superscalar SH-4 microprocessor

Functional verification of modern complex processors is a formidable and time consuming task. In spite of substantial manual effort, it is extremely difficult to systematically cover the corner cases of the control logic design, within a short processor design cycle. The SH4 processor is a dual issue superscalar RISC architecture with extensive hardware support for 3D graphics. We present the development of a semi automated methodology for functional verification. In particular, we elaborate a scheme to automatically generate test programs to verify the superscalar issue logic, bypass/multi bypass logic and stall logic, starting from the microarchitectural specification. Finally, we present the Random Test Generation methodology and the specific Random Test Generators.

Heterogeneous Multiprocessor on a Chip Which Enables 54x AAC-LC Stereo Encoding

A heterogeneous multiprocessor on a chip has been designed and implemented. It consists of 2 CPUs and 2 DRPs (Dynamic Reconfigurable Processors). The design of DRP was intended to achieve high-performance in a small area to be integrated on a SoC for embedded systems. Memory architecture of CPUs and DRPs were unified to improve programming and compiling efficiency. 54times AAC-LC stereo encoding has been enabled with 2 DRPs at 300 MHz and 2 CPUs at 600 MHz.

Design rule for frequency-voltage cooperative power control and its application to an MPEG-4 decoder

Frequency-voltage cooperative power control (FVC) is considered a powerful method to reduce the power consumption of a program, because it utilizes the information of software loads dynamically. The authors first show through a mathematical analysis that FVC with only two frequency-voltage sets is sufficient for current low-Vdd CPU chips. Then we show an experimental result that FVC feedback control on an MPEG-4 video decoder can reduce the power to one-fourth.