Fumio Yuki

A 12.3-mW 12.5-Gb/s Complete Transceiver in 65-nm CMOS Process

A 12.3-mW 12.5-Gb/s complete transceiver based on the 65-nm standard digital CMOS process was developed. The chip includes a clock-and-data-recovery (CDR) device, a multiplexer/demultiplexer (MUX/DEMUX), and a global clock-distribution network. To reduce power consumption, a low-swing voltage-mode driver with pulse-current boosting and an LC resonant-clock distribution with distributed on-chip inductors are used in the transmitter, while a symbol-rate phase detector (SPD) using a three-stage sense amplifier and phase-rotating phase-locked loop (PLL) with variable delay are used in the receiver. The transceiver operates at a bit error rate (BER) of 10-12 or less through a 20-cm test board with total attenuation of -12.1 dB while consuming power of 0.98 mW/(Gb/s) per transceiver.

A Compact 4

A compact parallel optical receiver consisting of a four-channel 25-Gb/s CMOS transimpedance-amplifier (TIA) array and a PIN-PD array for board-to-board optical interconnects was developed. Both arrays are directly mounted on a multi-layer ceramic package. The 25-Gb/s TIA array was fabricated by using 65-nm CMOS technology. To improve gain flatness and reduce inter-symbol interference caused by insertion loss, a gain-stage amplifier with flat frequency response and a 50-Ω output driver with an analogue equalizer were implemented in the TIA array. The TIA array achieves transimpedance gain of 69.8 dBΩ, bandwidth of 22.8 GHz, and gain flatness of ±2 dB after equalizing the effect of insertion losses at the input and output ports. A compact 100-Gb/s CMOS optical receiver is composed of a four-channel 25-Gb/s PIN-PD and the TIA array mounted on a 16-mm-square multi-layer low-temperature on-fired ceramic (LTCC) package. To alleviate the inner-channel crosstalk, the output signal lines from the PIN-PD array are connected to the TIA array through the coplanar lines, which are sandwiched by the upper and lower ground layers and the right-and-left ground lines. The optical receiver demonstrates negligible inter-channel crosstalk of less than -17 dB at operation frequency up to 25 GHz. Its measured sensitivity for a solitary signal input at 10-12 BER is -8.1 dBm, and its crosstalk between adjacent channels is 0.8 dB. Moreover, its power dissipation is only 3.0 mW/Gb/s at a data rate of 25 Gb/s, and its total power consumption (including that of the equalizer function) is low, i.e., 295 mW.

\, \times \,

For the people involved with multi-Gb/s chip-to-chip serial links, reducing power dissipation per Gb/s to less than 1mW/(Gb/s) (i.e., 1pJ/b) has been a long-held goal. Several years ago, the power dissipation of these links was in the range of about 10 to 20mW/(Gb/s). In 2007, Poulton et al. developed a 14mW 6.25Gb/s transceiver with power efficiency of 2.2mW/(Gb/s) [1]. Thereafter, there were some efforts aiming to reduce power of each building block in a transceiver [2, 3]. This paper presents a 12.3mW 12.5Gb/s complete transceiver (including CDR, MUX/DEMUX, and global clock distribution)in 65nm CMOS with power efficiency of 0.98mW/(Gb/s). To achieve low power, a resonant-clock distribution with distributed on-chip inductors and a low-swing voltage-mode driver with pulse-current boosting are used in the transmitter, while a symbol-rate comparator/phase detector using 4-stage sense amplifier and phase-rotating PLL with variable delay are used in the receiver.

25-Gb/s 3.0 mW/Gb/s CMOS-Based Optical Receiver for Board-to-Board Interconnects

This paper describes a 2.5-Gb/s/ch digital data recovery (DR) circuit for the SFI-5 interface. Although minimizing the circuit area has become critical in multibit interfaces such as the SFI-5, few studies have proposed a practical method of reducing the area of data recovery circuits. We introduce a digital-PLL-type DR circuit design with eye-tracking, which we developed to minimize the circuit area and power consumption without degrading tolerance against jitter. This novel method of data recovery enabled us to simplify the circuit design against process, voltage, and temperature variations. Design considerations on how to eliminate high-frequency jitter and how to track long-term wander are described. The design for 2.5-GHz clock distribution is also discussed. The area of the DR circuit, fabricated with 0.18-/spl mu/m SiGe BiCMOS technology, is 0.02 mm/sup 2//ch, and its power consumption is 50 mW/ch at 1.8 V. The measured tolerance against jitter at 2.5 Gb/s is 0.7 UI peak-to-peak, which satisfies the jitter specifications for the SFI-5.

A 12.3mW 12.5Gb/s complete transceiver in 65nm CMOS

IT systems such as servers and routers need high-speed lower- power area-efficient chip-to-chip interconnections through backplane boards. These interconnections must overcome signal degradation due to the large insertion loss of low-cost boards. In this work, a 90nm CMOS 8Gb/s transceiver is developed. A TX 5- tap FFE, an RX analog equalizer, and a 2-tap DFE combined with a 2-threshold eye-tracking CDR achieve a BER of less than 10-12 through a 160cm backplane board with -36.8dB loss at 4GHz and a transceiver power consumption of 232mW (transmission efficiency of 1.2Gb/sxdB/mW).

A 50-mW/ch 2.5-Gb/s/ch data recovery circuit for the SFI-5 interface with digital eye-tracking

A one-chip optical transceiver for board-to-board transmission was developed by integrating an analog frontend (FE) with a data-format-conversion (DFC) block in 65-nm CMOS process technology. It was experimentally demonstrated that this transceiver can convert 10x 6.25-Gb/s electrical signals to 4x 25-Gb/s optical signals with 25% redundancy that improves resilience against possible laser diode (LD) failure. To alleviate degradation of the optical link due to power-supply variations, a power-supply-noise-tolerant 25-Gb/s analog FE (consisting of a TIA with a noise canceller and a fully differential LD driver) is proposed. The noise canceller can keep the power-supply variation below 0.2 mV at frequencies down to 1 MHz, and the fully differential LD driver can keep power-supply current variation below 0.64 mApp/ch, despite a large modulation current of 20 mApp. As for the transmission performance of the transceiver, eye diagrams experimentally confirmed 25-Gb/s and 6.25-Gb/s data-transmission rates. A 25-Gb/s optical-link test on the transceiver demonstrated error-free operation at -6.1-dBm OMA. Moreover, an image-transfer test on the transceiver operating at a data rate of 20 Gb/s through a 100-m multi-mode fiber was demonstrated. Total power consumption of the transceiver (including optics) was 2.2 W at full-channel operation.

An 8Gb/s Transceiver with 3×-Oversampling 2-Threshold Eye-Tracking CDR Circuit for -36.8dB-loss Backplane

A one-chip transceiver was developed for optical backplanes by integrating an analog FE with data format conversion in 65-nm CMOS. 10×6.25Gb/s electrical signals were converted to 4×25Gb/s optical signals with 25% redundancy to improve resilience against possible LD failure. To alleviate degradation of the optical link due to power-supply variations, a TIA with a noise canceller and a fully differential LDD are proposed. The noise canceller decreases power-supply variations by 98%. Total power consumption was only 2.2W.

A 25-Gb/s 2.2-W 65-nm CMOS Optical Transceiver Using a Power-Supply-Variation-Tolerant Analog Front End and Data-Format Conversion

A prototype transceiver composed of a 1.3-μm-range lens-integrated laser diode and photodiode as well as a complementary metal-oxide-semiconductor (CMOS) laser diode driver and a CMOS transimpedance amplifier for high-speed optical interconnections was developed. It demonstrated 25-Gb/s error-free 100-m multimode fiber transmission, with power dissipation of only 9 mW/Gb/s, for the first time.

A 25-Gb/s 2.2-W optical transceiver using an analog FE tolerant to power supply noise and redundant data format conversion in 65-nm CMOS

A compact 25-Gbps × 4-channel optical transceiver has been fabricated for optical backplane systems. Power consumption was as low as 20 mW/Gbps. A transmission experiment was successfully conducted at 25 Gbps.

25-Gb/s 100-m MMF Transmission Using a Prototype 1.3-

Photonic technology is an important solution to achieve power-saving routers/switches for green networks. As networking is a worldwide matter, and as the power consumed by routers and switches is rapidly increasing, power-efficient green networks have become a subject of great interest. The main issue of green networking is relieving the increasing power consumption, and photonic technologies will be effective for such issue. Photonic technologies are low-power external input/output (I/O) port and internal interconnection subsystem, which contributes to reduce power consumption of routers and switches. For the external I/O port, 100-Gb Ethernet technologies, which use high-speed and low-power optical and electrical CMOS devices, will be described. Also, we describe the power-saving photonic technologies for interconnection subsystems for network equipments. This optical interconnection (optical backplane) technology also requires optical and electrical devices, which are compact in size, high speed, and operate at low power. This interconnection realizes a highly energy efficient router/switch with advanced network functions.