Goichi Ono

A 1000-MIPS/W microprocessor using speed adaptive threshold-voltage CMOS with forward bias

Substrate bias is continuously controlled from -1.5 V (backward bias) to 0.5 V (forward bias) to compensate for fabrication fluctuation, supply voltage variation, and operating temperature variation. A speed-adaptive threshold-voltage (SA-Vt) CMOS with forward bias is used in a 4.3M transistor microprocessor. The SA-Vt CMOS with forward bias occupies 320/spl times/400 /spl mu/m/sup 2/ and consumes 4 mA. The processor provides 400 VAX MIPS at 1.5 to 1.8 V with 320 to 380mW dissipation. It achieves >1000-MIPS/W performance.

A 12.3-mW 12.5-Gb/s Complete Transceiver in 65-nm CMOS Process

A 12.3-mW 12.5-Gb/s complete transceiver based on the 65-nm standard digital CMOS process was developed. The chip includes a clock-and-data-recovery (CDR) device, a multiplexer/demultiplexer (MUX/DEMUX), and a global clock-distribution network. To reduce power consumption, a low-swing voltage-mode driver with pulse-current boosting and an LC resonant-clock distribution with distributed on-chip inductors are used in the transmitter, while a symbol-rate phase detector (SPD) using a three-stage sense amplifier and phase-rotating phase-locked loop (PLL) with variable delay are used in the receiver. The transceiver operates at a bit error rate (BER) of 10-12 or less through a 20-cm test board with total attenuation of -12.1 dB while consuming power of 0.98 mW/(Gb/s) per transceiver.

Electric-energy generation using variable-capacitive resonator for power-free LSI: efficiency analysis and fundamental experiment

A power generator based on a vibration-to-electric energy converter using a variable-resonating capacitor is experimentally demonstrated. The generator consists of a complete system with a mechanical-variable capacitor, a charge-transporting LC tank circuit and an externally powered timing-capture controller. A practical design methodology to maximize the efficiency of the vibration-to-electric energy generation system is also described. The efficiency of the generator is estimated based on three factors: the mechanical-energy loss, the charge-transportation loss, and the timing-capture loss. Through the mechanical-energy analysis, the optimum condition for the resonance is found. The parasitic elements in the charge transporter and the timing management of the capture scheme dominate the generation efficiency. These analyses enable the optimum design of the energy-generation system. An experimentally fabricated and measured generator theoretically has a maximum power of 580 nW; the measured power is 120 nW, so conversion efficiency is 21%. This results from a 43% mechanical-energy loss and a 63% charge-transportation loss. The timing-capture scheme is manually determined and externally powered in the experiment, so its efficiency is not considered. With our result, a new system LSI application with an embedded power source can be explored for the ubiquitous computing era.

Threshold-voltage balance for minimum supply operation [LV CMOS chips]

The difference between the threshold voltages V/sub t/ of pMOS and nMOS transistors is a critical issue in the low-voltage operation of CMOS circuits. The pMOS/nMOS V/sub t/ balancing profit is analyzed in terms of subthreshold leakage current and the performance of CMOS LSIs and the minimum supply voltage of logic circuits. Matching the pMOS/nMOS V/sub t/ improves LSI performance and reduces the lowest supply voltage by 0.15 V. We propose a new concept of body bias management that uses forward biasing, fluctuation compensating, and V/sub t/ matching technologies to resolve the issue.

A 12.3mW 12.5Gb/s complete transceiver in 65nm CMOS

For the people involved with multi-Gb/s chip-to-chip serial links, reducing power dissipation per Gb/s to less than 1mW/(Gb/s) (i.e., 1pJ/b) has been a long-held goal. Several years ago, the power dissipation of these links was in the range of about 10 to 20mW/(Gb/s). In 2007, Poulton et al. developed a 14mW 6.25Gb/s transceiver with power efficiency of 2.2mW/(Gb/s) [1]. Thereafter, there were some efforts aiming to reduce power of each building block in a transceiver [2, 3]. This paper presents a 12.3mW 12.5Gb/s complete transceiver (including CDR, MUX/DEMUX, and global clock distribution)in 65nm CMOS with power efficiency of 0.98mW/(Gb/s). To achieve low power, a resonant-clock distribution with distributed on-chip inductors and a low-swing voltage-mode driver with pulse-current boosting are used in the transmitter, while a symbol-rate comparator/phase detector using 4-stage sense amplifier and phase-rotating PLL with variable delay are used in the receiver.

Accurate Wireless Location/Communication System With 22-cm Error Using UWB-IR

We propose a high-accuracy, low-cost UWB-IR wireless location system based on the quasi TDOA method. The system consists of anchor nodes, a synch node and a location server. The anchor nodes synchronize each other as regulated by the synch node so that synchronization is always precise in the location process. To make the anchor node simple, the location system uses acquisition and tracking functions that can measure the time when a signal is received as accurately as pulse signal width. In addition, we performed a wireless location experiment indoors and the average error of the location measurement was 22-cm

Electric power generation using piezoelectric resonator for power-free sensor node

This paper describes a power-free sensor node operated by ambient vibration energy. An electric power generator is based on a vibration-to-electric energy converter using a piezoelectric resonator. The power generator consists of a piezoelectric resonator, and a power control circuit for recharging. Key technologies are the analysis model that compensates for inertia moment of the piezoelectric resonator, and the power control circuit that stores scavenged current charge to supply instant power for radio communication. The condition optimization for the size of the resonator is match of resonance frequency, which achieves highly efficient resonator. The power control circuit that stores electric power of the 180 /spl mu/W and supplies electric power of 30 mW. As a result, the power generator achieves 5 minute intermittent operation of a power-free sensor node.

100GbE PHY and MAC layer implementations

This article discusses the logical implementation of the media access control and the physical layer of 100 Gb/s Ethernet. The target are a MAC/PCS LSI, supporting MAC and physical coding sublayer, and a gearbox LSI, providing 10:4 parallel lane-width exchange inside an optical module. The two LSIs are connected by a 100 gigabit attachment unit interface, which consists of ten 10 Gb/s lines. We realized a MAC/PCS logical circuit with a low-frequency clock on a FPGA, whose size is 250 kilo LUTs with a 5.7 Mbit RAM, and the power consumption of the gearbox LSI estimated to become 2.3 W.

1-cc Computer: Cross-Layer Integration With UWB-IR Communication and Locationing

The first one-cc or one-cubic-centimeter computer (OCCC) that integrates a sensor, ultra-wideband impulse radio (UWB-IR) transmitter, computing engine, and battery is demonstrated. Cross-layer integration includes SPIKE control, which achieves a record low power communication of 3.4-nW/bps with reduced operating time. Miniaturization techniques, such as wafer-level chip-size packaging and flip-chip packaging, were used to shrink the module to a volume of 1 cc. The fabricated OCCC is shown to operate as designed, communicating at distances of 10 and 30 m and at transmission rates of 10.7 Mbps and 258 kbps, respectively. The life of a 150-mAh battery in an OCCC that operates once every five minutes is estimated to be longer than 10 years. The communication-location integration (CLI) technique, which achieves 22-cm location accuracy with only a 1.3% chip area overhead, is also proposed.

A CMOS UWB-IR Receiver Analog Front End with Intermittent Operation

A low power receiver analog front end (AFE) for ultra-wideband impulse radio (UWB-IR) was developed in 0.18 mum CMOS. All circuits of the receiver AFE operate intermittently with a sampling clock of an analog-digital converter (ADC). The sampling rate of the ADC is equal to pulse repetition frequency of the received signals. Power consumption of the receiver AFE is decreased 60% by intermittent operation without degrading of receiver sensitivity. As a result, the power consumption of the receiver AFE is 38 mW at 258 kbps data rate.