Fumio Yuuki

A new assembly architecture for multichannel single mode-fiber-pigtail LD/PD modules

A novel assembly architecture is developed for alignment and soldering between single-mode (SM) fiber arrays and laser-diode/photodiode (LD/PD) arrays. The image position detection method, by eliminating degrees of freedom for alignment, improves assembly throughput to twice that of conventional assembly architecture. The thermal shrinkage compensation method achieves high-precision soldering by canceling misalignments due to thermal shrinkage of assembly equipment and solder volume. As a result, assembly, through all processes, achieves +or-1.5- mu m precision, which corresponds to a +or-1-dB fluctuation of coupling efficiency. Based on this architecture, eight-channel SM-fiber-pigtail LD/PD modules were successfully assembled.<<ETX>>

25 Gb/s parallel CMOS-based optical receiver with very low inter-channel crosstalk and power consumption

An integrated 100-Gb/s receiver, which consists of a four-channel 25 Gb/s CMOS trans-impedance amplifier and PIN-PD arrays, was fabricated for high sensitivity (−8.1 dBm), small inter-channel crosstalk (0.8 dB), and low-power (3.0 mW/Gb/s) operation.

Impedance matching method for jitter reduction of 28Gbps retimer

We developed a long channel backplane 28 Gbps transmission technology for next-generation high-speed I/O applications. To achieve long-channel backplane traces at 28 Gbps, main jitter sources such as ISI, crosstalk, power supply noise, and circuit origin including random jitter need to be drastically reduced. Among these, ISI is the largest jitter source. It is important to not only compensate for loss of channel but also reduce reflections due to impedance mismatch. Therefore, we proposed a low-jitter implementation technology for a package (PKG) and a print circuit board (PCB). This technique is a method to buffer the impedance mismatch by the impedance drop of a solder ball at high-speed transmission. By using the proposed technique, the ISI jitter can reduce 1 ps and EYE opening margin can be made larger than 0.04 UI.

Transmission design technique for 25-Gbps retimer

We developed a long channel backplane 25-Gbps transmission technology for next-generation high-speed I/O applications. To achieve long-channel backplane traces at 25 Gbps, main jitter sources such as ISI, crosstalk, power supply noise, and circuit origin including random jitter need to be drastically reduced. Among these, ISI is the largest jitter source. When multiple equalization devices are used, the distribution method of the quantity of equalization is a problem. We therefore reduce ISI jitter and suggest the most suitable equalization technique to improve transmission margin. Our strategy is to optimize distribution of the quantity of equalization so that jitter is minimized. We were able to realize a small jitter of just 5.5 ps, and design characteristics in good agreement with the measurements were demonstrated by use of the proposed technique.