Masayoshi Yagyu

Design, fabrication and evaluation of a 5-inch wafer scale neural network LSI composed on 576 digital neurons

A wafer-scale-integration (WSI) neural network has been fabricated and evaluated. 576 digital neurons are integrated and interconnected with each other on a 5-in silicon wafer by using 0.8-μm CMOS. Neural functions are faithfully mapped to binary digital circuits. The 9-bit output and the 8-bit synapse weight of each neuron are variable. A time-sharing digital bus architecture overcomes the disadvantage of digital neuron circuits. This WSI neural network can be connected with a host computer and used for a wide range of artificial neural networks. The 16-city traveling salesman problem could be solved in less than 0.1 s by using this network. This speed was 10 times faster than a Hitachi supercomputer. Larger artificial neural networks can be realized by simply connecting WSIs

A self-learning digital neural network using wafer-scale LSI

A large-scale, dual-network architecture using wafer-scale integration (WSI) technology is proposed. By using 0.8 mu m CMOS technology, up to 144 self-learning digital neurons were integrated on each of eight 5 in silicon wafers. Neural functions and the back-propagation (BP) algorithm were mapped to digital circuits. The complete hardware system packaged more than 1000 neurons within a 30 cm cube. The dual-network architecture allowed high-speed learning at more than 2 gigaconnections updated per second (GCUPS). The high fault tolerance of the neural network and proposed defect-handling techniques overcame the yield problem of WSI. This hardware can be connected to a host workstation and used to simulating a wide range of artificial neural networks. Signature verification and stock price prediction have already been demonstrated with this hardware. >

A self-learning neural network composed of 1152 digital neurons in wafer-scale LSIs

The design, fabrication, and evaluation of a compact self-learning neural network made up of more than 1000 neurons are described. A time-sharing bus architecture decreases the number of circuits required and makes possible flexible and expandable networks. Neural functions and the back propagation (BP) algorithm were mapped to binary digital circuits. A dual-network architecture allows high-speed learning. This hardware can be connected to a host workstation and used for a wide range of artificial neural networks. Signature verification and stock price prediction have already been demonstrated with this hardware. The peak learning speed was about 10 times faster than BP simulation by an S-820 Hitachi supercomputer.<<ETX>>

An 8Gb/s Transceiver with 3×-Oversampling 2-Threshold Eye-Tracking CDR Circuit for -36.8dB-loss Backplane

IT systems such as servers and routers need high-speed lower- power area-efficient chip-to-chip interconnections through backplane boards. These interconnections must overcome signal degradation due to the large insertion loss of low-cost boards. In this work, a 90nm CMOS 8Gb/s transceiver is developed. A TX 5- tap FFE, an RX analog equalizer, and a 2-tap DFE combined with a 2-threshold eye-tracking CDR achieve a BER of less than 10-12 through a 160cm backplane board with -36.8dB loss at 4GHz and a transceiver power consumption of 232mW (transmission efficiency of 1.2Gb/sxdB/mW).

Measurement techniques for on-chip power supply noise waveforms based on fluctuated sampling delays in inverter chain circuits

To evaluate an on-chip power supply noise waveforms for power integrity design, we have developed a technique for measuring on-chip voltage waveforms. To overcome trade-offs in voltage resolution and the measurable frequency band, we designed inverter chain circuits that change the lengths of series inverters: a short chain provides low frequency and high resolution, while a long chain provides high frequency and low resolution. We measured on-chip noise waveforms using a 90 nm CMOS test chip with a 50 -inverter chain circuit as small as 320 square micrometers, confirming that the circuit could achieve a voltage resolution of 1 mV and temporal resolution of 20 ps. The amplitude of the noise waveform generated by the noise source circuits is proportional to the activating ratio of the source, although resonance frequencies are virtually the same - 160 MHz - when the activating ratios change.

Chip-package-PCB co-simulation for power integrity design at the early design stage

We investigated a chip-package-PCB co-simulation method for power integrity design at the early design stage. Due to the number of design parameters that need to be surveyed to optimize power integrity at this stage, the method requires fast power integrity analysis and a convenient way to revise design parameters. By applying a PEEC method with different mesh sizes for each component and reducing the input cost for the power and ground plane layout, we can reduce simulation costs with permissible levels of simulation error.

Modeling of chip-package resonance in power distribution networks by an impulse response

This paper proposes a method for modeling chip-package resonance using impulse response. To extract chip and package electrical circuit parameters, we assume a circuit equivalent to the loop from the chip to the package decoupling capacitor as the RL-RC parallel circuit and convert it into an RLC parallel circuit. We apply this method to devise an electrical circuit model capable of expressing chip-package resonance with high accuracy, as confirmed by experimental results.

A low-power write driver for hard disk drives

This paper describes a new low-power write driver circuit for mobile hard disk drive preamplifiers. To achieve low power consumption, we developed a write driver circuit with a single-stage MOS transistor as the current driver, which both switches and controls the write current. We also developed a reflection cancellation method to suppress the distortion of the write current waveform during write transition. Fabricated by 0.35-/spl mu/m SOI-BiCMOS technology, this write driver circuit dissipates low power, 380 mW (at 100 MHz).

PCB trace modeling and equalizer design method for 10 Gbps backplane

This paper discusses accurate PCB modeling methods for 10 Gbps differential signal traces. We added two approaches to the conventional modeling method: (1) We simulated the glass cloth and epoxy distribution in the PCB dielectric to simulate common/differential mode conversion noise (SCD21). (2) We applied a frequency-dependent dielectric constant to the electromagnetic analysis model based on a Djordjevic-Sarkar model to introduce a frequency-dependent group delay. Applying these two additional modeling elements, we obtained accurate SCD21 and jitter properties consistent with measurement results. We also demonstrated an equalizer design based on the improved PCB model. By flattening the frequency dependence of the group delay as well as trace losses for the transmission paths, including the equalizer, by adjusting the properties of the peaking amplifier for the equalizer circuit, we reduced jitter by up to 10 ps for 10 Gbps signalling.

Impulse response of on-chip power supply networks under varying conditions

This paper presents a method for modeling chip-package resonance using impulse response and for measuring waveforms under varying conditions. We evaluated chip-package resonance with the following variations in conditions: (i) with and without on-package capacitors; (ii) differing positions on the chip; (iii) differing points of observation outside the chip (probe points for the package capacitor and bypass capacitor on the printed circuit board); (iv) circuit activating ratios varying from 11% to 100%. The results suggest that a circuit equivalent to our test chip can be expressed as a single lumped circuit. The results also demonstrate the effectiveness of on-package capacitors in reducing extra anti-resonance.