Fumitoshi Yamamoto
Mitsubishi
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Publication
Featured researches published by Fumitoshi Yamamoto.
international symposium on power semiconductor devices and ic's | 2002
Tomohide Terashima; Fumitoshi Yamamoto; Kenichi Hatasako; Shiro Hine
The new 0.5 /spl mu/m design rule 120 V class BiCMOS and DMOS (120 V BiC-DMOS) process is developed by slight modifications from the 90 V BiC-DMOS process. The extra-one mask is added to enforce the isolation. Moreover, all the 5 V 90 V class devices are still included in this process. Improved edge termination structure brings 135 V breakdown voltage and 0.41 /spl Omega/ mm/sup 2/ in DMOS (vertical). DMOS (full isolation type) is also realized by using the RESURF (reduced surface field) structure. The combination of p/sup -/ LDD (lightly doped drain) and rounded P well are used for 120 V PMOS and 120 V field PMOS.
Archive | 1999
Fumitoshi Yamamoto; Tomohide Terashima
Archive | 1999
Yasunori Yamashita; Tomohide Terashima; Fumitoshi Yamamoto
Archive | 1998
Fumitoshi Yamamoto
Archive | 2003
Yasunori Yamashita; Fumitoshi Yamamoto; Tomohide Terashima
Archive | 1998
Fumitoshi Yamamoto; Tetsuo Higuchi
Archive | 1998
Fumitoshi Yamamoto; Tomohide Terashima
Archive | 2003
Keiichi Furuya; Fumitoshi Yamamoto; Tomohide Terashima
Archive | 2002
Fumitoshi Yamamoto; Tomohide Terashima
Archive | 2000
Fumitoshi Yamamoto; Tomohide Terashima
