Tomohide Terashima

Great impact of RFC technology on fast recovery diode towards 600 V for low loss and high dynamic ruggedness

In the fast recovery operation of Free-wheeling Diode (FWD), to reduce voltage surge “snap-off”, we propose the Relaxed Field of Cathode (RFC)-planar anode diode in the range of 600 V to 1700 V. RFC effect is described by the parallel connection of pin diode and pnp transistor in as a single chip solution. Its structure is realized by our thin wafer process technology utilizing the backside lithography to make p/n alternating pattern after thining the wafer. As the result, our RFC diode up to 1700 V has the following three advantages comparing with the conventional one: (a) 40% lower recovery loss (EREC), 30% lower forward voltage drop (VF), (b) a large recovery Safe Operating Area (SOA) with the high peak power density of 1.4W/cm2 and (c) easiness to adjust a lower crosspoint below rated current density in the output I-V. Therefore, the proposed RFC diode has a great potential as the next generation Si FWD in the all voltage range.

LPT(II)-CSTBT™(III) for High Voltage application with ultra robust turn-off capability utilizing novel edge termination design

In this paper, the phenomena of current crowding and impact ionization in edge termination of High-Voltage (HV) LPT(II)-CSTBT™(III) is investigated. It is discovered for the first time that these two phenomena act as separated heat sources and induce one local hot spot which causes the thermal destruction in the edge termination during large current and high voltage turn-off switching. A novel edge termination design called “Partial P Collector” is proposed and evaluated. The novel design reduces current crowding and relaxes electric field in the edge termination. Simulated and measured results show that the failure mode of the novel design is determined by current filament phenomenon inside active cell region. It concludes that HV LPT(II)-CSTBT™(III) utilizing Partial P Collector edge termination design has ultra robust turn-off capability without deteriorating other electrical performances.

Next generation 600V CSTBT™ with an advanced fine pattern and a thin wafer process technologies

In this paper, we present the characteristics of a fabricated 600V CSTBT™ as the next generation IGBT. The techniques applied this novel device include about half-size shrinkage of the transistor unit cell with a fine pattern process and an LPT (Light Punch Through) structure utilizing an advanced thin wafer process technology. As a result, these techniques brought a significant reduction of the Vce(sat) and the Eoff. The Vce(sat)-Eoff trade-off relationship of the proposed CSTBT has been improved by approximately 20% compared to the conventional one possessing wide SOA (Safe Operating Area) enough to device applications.

Relaxation of current filament due to RFC technology and ballast resistor for robust FWD operation

We have investigated the destruction mechanism of High Voltage (HV) Free Wheeling Diodes (FWD) during a reverse recovery operation. The most possible mode of the destruction phenomena originate in local heating due to current filament at the edge portion of the active area. To achieve a large reverse recovery Safe Operation Area (SOA), we focus on the boundary region between the active area and the termination area. To enforce our Relaxed Field of Cathode (RFC) concept [1, 2], it is more effective for the wider SOA to place a ballast resistance for avoiding the current from crowding around the anode region in the top surface of the diode.

A novel driving technology for a passive gate on a Lateral-IGBT

This paper presents a novel technology for automatic driving of the passive PMOS to improve a Lateral-IGBT switching performance. Though the former technology, which we had introduced [4, 5], has very simple driving circuitry, it still needs some additional process or structural change. The novel technology eliminates these remained problems without decrease in device performance. Simulation results indicate advantage of the novel technology in total performance compared with results of the former technology. Besides, experimental results of the prototype IPD with the novel technology have indicated improved switching performance distinctly.

Structure of 600 V IC and a new voltage sensing device

A novel high-voltage isolation structure which has a 600-V breakdown voltage has been developed. This structure realizes improved stability of the breakdown voltage by combining reduced surface field (RESURF) technology with a multiple floating field plate (MFFP) and an n/sup +//n/sup -/ buried layer. A high-voltage n-ch MOSFET was realized by combining a lateral DMOS structure with the high-voltage isolation structure. A high-voltage p-ch MOSFET was realized by combining the offset gate using the polysilicon layer of the MFFP. A novel voltage sensing device was constructed by the addition of a p-type floating layer to the high-voltage isolation structure. Its output voltage is automatically restricted within the logic power supply level.<<ETX>>

Analysis of a drain-voltage oscillation of MOSFET under high dV/dt UIS condition

In this paper, we investigate a mechanism of drain-voltage oscillation of MOSFET under high dV/dt UIS condition by using numerical simulation and experiments. One of the trigger events of the oscillation is found to be the current path switching between the active region and the termination region with close BVDSS characteristics. By optimizing the device parameters to make appropriate the BVDSS balance, avalanche capability is improved over ~ 40%, enabling the oscillation-free turn-off.

A 0.8 /spl mu/m high voltage IC using newly designed 600 V lateral IGBT on thick buried-oxide SOI

We have demonstrated that the developed process has a breakdown voltage of higher than 600 V with use of thick buried-oxide and thin SOI. From both experiments and simulations, the cylindrical structure in the LIGBTs shows the best performance; it improves the latch-up tolerance without the increase of on-state voltage. Moreover, the process we have developed is completely compatible with an existing 5 V, 0.8 /spl mu/m CMOS process.

Characterization and Modeling of a 1.2-kV 30-A Silicon-Carbide MOSFET

This paper describes a novel compact model for a SiC-MOSFET. The model is useful to achieve accurate simulation of output characteristics from a linear region to a saturation region, selecting both gate-source voltage and temperature as parameters. In order to construct the model systematically, attention is paid to a physics-based modeling procedure with channel mobility as an adjustable parameter. The model also features characterization and modeling of an internal drain-gate capacitor. The model shows fairly good agreement in the output characteristics and the dynamic behavior of both gate drive circuit and main power circuits between the experimental and simulated results. This successful validation indicates that this model offers a promising circuit-based simulation tool for designing whole power conversion systems using SiC-MOSFETs.

An improvement on p-channel SOI LIGBT by adopting slit type p-drift structure

A new p-channel slit type p-drift lateral IGBT (p-ch SD-LIGBT) is described. This device is fabricated with thick buried-oxide SOI, using 0.8 /spl mu/m CMOS process. The improvement of slit type p-drift structure makes it possible to realize excellent characteristics in the trade-off between breakdown voltage and on-state current relationship compared with p-ch conventional SOI-LIGBT. Furthermore, measured characteristics are reported for p-ch SOI-LIGBT with a breakdown voltage of more than 500 V for the first time.