Fumiyoshi Matsuoka

Numerical analysis of alpha-particle-induced soft errors in floating channel type surrounding gate transistor (FC-SGT) DRAM cell

This paper clarifies alpha-particle-induced soft error mechanisms in floating channel type surrounding gate transistor (FC-SGT) DRAM cells. One FC-SGT DRAM cell consists of an FC-SGT and a three-dimensional (3-D) storage capacitor. The cell itself arranges bit line (BL), storage node and body region in a silicon pillar vertically and achieves cell area of 4F/sup 2/ (F: feature size) per bit. In FC-SGT DRAM cells, the parasitic bipolar current is a major factor to cause soft errors. When an alpha particle penetrates the silicon pillar, generated electrons are collected to the storage node or BL due to the tunneling and diffusion mechanisms. On the other hand, holes are swept into the body region and accumulated. Consequently, the current flows not only in the surface but also in the entire body region due to the floating body effect. This parasitic bipolar current becomes the largest when an alpha particle penetrates the silicon pillar along the vertical axis. However, in case of FC-SGT DRAM cells, the surrounding gate structure can suppress the floating body effect compared with floating channel type SOI DRAM cells. As a result, the loss of the stored charge in the storage capacitor can be drastically decreased by using FC-SGT DRAM cell. Therefore, FC-SGT DRAM is a promising candidate for future high-density DRAMs having high soft-error immunity.

Device design guidelines for FC-SGT DRAM cells with high soft-error immunity

This paper describes the device design guidelines for floating channel type surrounding gate transistor (FC-SGT) DRAM cells with high soft-error immunity. One FC-SGT DRAM cell consists of an FC-SGT and a three-dimensional storage capacitor. The cell itself arranges the bit line (BL), storage node, and body region in a silicon pillar vertically and hence, achieves a cell area of 4F/sup 2/ (F: feature size) per bit. A thin-pillar FC-SGT with a metal gate can maintain a low leakage current without using a heavy doping concentration in the body region. Furthermore, as the silicon pillar thickness is reduced, the device enters into the fully depleted operation and as a result can realize excellent switching characteristics. In FC-SGT DRAM cells, the parasitic bipolar current is a major factor that causes soft errors to occur. However, the parasitic bipolar current can be suppressed and its duration can be shortened as the silicon pillar thickness is reduced. As a result, the amount of stored charge lost in the storage capacitor can be effectively decreased by using a thin-pillar FC-SGT. In the case of a 10-nm-thick FC-SGT, the amount lost due to the parasitic bipolar current is decreased to about 28% of that due to the leakage current. Therefore, FC-SGT DRAM is a promising candidate for future nanometer high-density DRAMs having high soft-error immunity.

An Analysis of the Effect of Surrounding Gate Structure on Soft Error Immuniy

This paper clarifies the effect of surrounding gate structure on soft error immunity in floating body type devices. Alpha-particle-induced soft error simulations were performed with surrounding gate, tri-gate and double gate transistors as transfer devices of DRAM cells. In case of surrounding gate transistor (SGT) cell, the loss of the stored charge in the storage node after an alpha-particle strike can be drastically reduced because the surrounding gate structure can suppress the floating body effect most efficiently by the highest controllability of the body potential compared with other gate structures. Therefore, SGT DRAM cell is a promising candidate for future high density DRAMs having high soft error immunity.