Hiroshi Sakuraba

0.18-/spl mu/m CMOS 10-Gb/s multiplexer/demultiplexer ICs using current mode logic with tolerance to threshold voltage fluctuation

A feedback MOS current mode logic (MCML) is proposed for the high-speed operation of CMOS transistors. This logic is more tolerant to the threshold voltage fluctuation than the conventional MCML and is suitable for gigahertz operation of deep-submicron CMOS transistors. Using this logic, 8:1 multiplexer (MUX) and 1:8 demultiplexer (DEMUX) ICs for optical-fiber-link systems have been fabricated with 0.18-/spl mu/m CMOS transistors. The ICs are faster than conventional CMOS MUX and DEMUX ICs and their power consumption is less than 1/4 of that of the conventional 10-Gb/s MUX and DEMUX ICs made using Si bipolar or GaAs transistors.

An on-chip 96.5% current efficiency CMOS linear regulator using a flexible control technique of output current

This paper proposes an on-chip 96.5% current efficiency CMOS linear regulator using a flexible control technique of output current (FCOC). By the use of the FCOC technique, the proposed circuit realizes flexible output current drive according to the load current variation. Therefore, the proposed linear regulator ran supply stable output voltage using the FCOC technique. The linear regulator is fabricated by double-metal 1.2-/spl mu/m CMOS technology. The number of transistors is 46 and the die size is 0.423 mm/sup 2/. The fabricated linear regulator achieves a fluctuation of output voltage less than 6.81 mV/sub p-p/ at a frequency of output current f(I/sub out/) ranging from 1.8 Hz to 100 MHz. Moreover, the fabricated on-chip CMOS linear regulator can achieve 96.5% current efficiency.

2.4F/sup 2/ memory cell technology with stacked-surrounding gate transistor (S-SGT) DRAM

This paper proposes 2.4F/sup 2/ memory cell technology with stacked-surrounding gate transistor (S-SGT) DRAM. One unit of the S-SGT DRAM is formed by stacking several SGT-type cells in series vertically. The SGT-type cell itself arranges gate, source, drain and plate on a silicon pillar vertically. Both gate and plate electrode surround the silicon pillar. Subsequently applied trench etching and sidewall spacer formation during S-SGT DRAM formation causes a step-like silicon pillar structure. Due to these steps, gate, plate and diffusion layer in one S-SGT DRAM unit are fabricated vertically by a self-aligned process. The cell size dependence of the self-aligned-type S-SGT DRAM was analyzed with regard to the above step widths and the number of cells in one unit. As a result, the cell design for minimizing the cell size of this device has been formulated. By using the proposed cell design, it is demonstrated by process simulation that the S-SGT DRAM in 0.5 /spl mu/m design rule can achieve a cell size of 2.4F/sup 2/, which is half of the cell size of a conventional SGT DRAM cell (4.8F/sup 2/). Therefore, the S-SGT DRAM is a promising candidate for future ultra high density DRAMs.

High-Performance Buried-Gate Surrounding Gate Transistor for Future Three-Dimensional Devices

We propose the buried-gate surrounding gate transistor (BG-SGT) as a high-performance transistor. The occupied area of BG-SGT can be shrunk to 50% of that of the planar transistor. Moreover, decreasing the body pillar size leads to a steep subthreshold slope. Because of these features, BG-SGT is extremely attractive for future three-dimensional devices.

New three-dimensional memory array architecture for future ultrahigh-density DRAM

In this paper, a three-dimensional (3-D) memory array architecture is proposed. This new architecture is realized by stacking several cells in series vertically on each cell located in a two-dimensional array matrix. Therefore, this memory array architecture has a conventional horizontal row and column address and new vertical row address. The total bit-line capacitance of this proposed architectures DRAM is suppressed to 37% of normal DRAM when one bit-line has 1-Kbit cells and the same design rules are used. Moreover, an array area of 1-Mbit DRAM using the proposed architecture is reduced to 11.5% of normal DRAM using the same design rules. This proposed architectures DRAM can realize small bit-line capacitance and small array area simultaneously. Therefore, this proposed 3-D memory array architecture is suitable for future ultrahigh-density DRAM.

Optimization of low temperature surface treatment of GaAs crystal

This paper reports the effects of a low temperature surface treatment under AsH3 overpressure on the GaAs regrown interface quality prepared by photostimulated molecular layer epitaxy. The regrown diode I–V characteristics are investigated as functions of treatment temperature, AsH3 pressure and treatment time. Optimized surface treatment conditions enable a good regrown interface to be obtained even at a lower temperature of ∼480°C than the conventional high temperature treatment at ∼600°C. The surface treatment mechanism is also discussed in combination with the results of X-ray photoemission spectroscopy and quadrupole mass analysis.

An analysis of program and erase operation for FC-SGT flash memory cells

The floating channel type surrounding gate transistor (FC-SGT) flash memory cell realizes high-speed bipolarity program and erase operations. In this investigation, the time dependence of the surface potential in the floating channel region, which strongly affects program and erase performance, is studied during program and erase operation. By analyzing the carrier generation processes in the floating channel region, the program and erase operation for FC-SGT flash memory cells is clarified.

A quantitative analysis of stress-induced leakage currents and extraction of trap properties in 6.8 nm ultrathin silicon dioxide films

An analytical model for the quantitative analysis of stress-induced leakage currents (SILC) in ultrathin silicon dioxide films is described, which enables the extraction of trap parameters, e.g., trap site location. Assuming a two-step trap-assisted inelastic tunneling mechanism, the conduction of electrons through the silicon dioxide film proceeds as follows: First, electrons tunnel from the cathode into neutral trap sites followed by an energy relaxation into the lowest available energy state of these trap sites. Finally, the electrons reach the anode by a direct tunneling process. We applied this model to the SILC characteristics of a stressed 6.8 nm ultrathin silicon dioxide film. The following parameters could be deduced: The trap sites are located at 4.47 nm relative to the cathode interface with a trapped sheet charge density of |6.54×10−8| C/cm2, and a trap state energy of 2.3 eV relative to the conduction band edge of the silicon dioxide.

A 10 Gb/s demultiplexer IC in 0.18 /spl mu/m CMOS using current mode logic with tolerance to the threshold voltage fluctuation

A 10 Gb/s 1:8 Demultiplexer (DEMUX) IC for optical-fiber-link systems uses a 0.18 /spl mu/m CMOS process for the first time. A differential logic like MOS current mode logic (MCML) is suitable for 10 Gb/s systems because of its switching speed and power consumption. The maximum operating frequency of MCML is, however, reduced by fluctuation of the threshold voltages (V/sub TH/) of the differential pair transistors. This V/sub TH/ fluctuation is a serious problem for deep submicron MOSFETs. The present circuit uses feedback MCML which is more tolerant to V/sub TH/ fluctuation than conventional MCML technology.

Surface reaction of trimethylgallium on GaAs

The surface reaction mechanism of Ga(CH3)3 (trimethylgallium: TMG) on GaAs during monolayer growth by molecular layer epitaxy was investigated by quadrupole mass spectroscopy. The desorbed species by the reaction of TMG on GaAs (001), (111)As, and (111)Ga surfaces have been studied by the quadrupole mass spectroscopy signals. At 420–510 °C, adsorbed monolayers of GaCH3 are formed on the GaAs (001) surface by sufficient TMG introduction. The adsorbed GaCH3 form Ga and CH3 with a time constant of 15–36 s in the transient state. Furthermore, the decomposition of TMG occurs on this adsorbed GaCH3 or Ga layer as the steady state reaction progresses and volatile GaCH3, Ga(CH3)2, and CH3 are produced. In the case of (111)As, TMG decomposed into Ga and CH3 above 480 °C, below which the volatile adsorbates GaCH3 and Ga(CH3)2 are formed. These adsorbates migrate on the surface and react with each other or with TMG, gradually decomposing into Ga. TMG adsorbs temporarily on the (111)Ga surface and decomposes into GaC...