G. Conte

A class of generalized stochastic Petri nets for the performance evaluation of multiprocessor systems

Generalized stochastic Petri nets (GSPNs) are presented and are applied to the performance evaluation of multiprocessor systems. GSPNs are derived from standard Petri nets by partitioning the set of transitions into two subsets comprising timed and immediate transitions. An exponentially distributed random firing time is associated with each timed transition, whereas immediate transitions fire in zero time. It is shown that GSPN are equivalent to continuous-time stochastic processes, and solution methods for the derivation of the steady state probability distribution are presented. Examples of application of gspn models to the performance evaluation of multiprocessor systems show the usefulness and the effectiveness of this modeling tool. 15 references.

Modelling with Generalized Stochastic Petri Nets

From the Publisher: nThis book presents a unified theory of Generalized Stochastic Petri Nets (GSPNs) together with a set of illustrative examples from different application fields. The continuing success of GSPNs and the increasing interest in using them as a modelling paradigm for the quantitative analysis of distributed systems suggested the preparation of this volume with the intent of providing newcomers to the field with a useful tool for their first approach. Readers will find a clear and informal explanation of the concepts followed by formal definitions when necessary or helpful. The largest section of the book however is devoted to showing how this methodology can be applied in a range of domains.

A class of generalised stochastic petri nets for the performance evaluation of multiprocessor systems

Graph models have been proposed by many authors as a useful tool for the analysis of peculiar features of computer systems such as concurrency, synchronization, communication, and cooperation among subsystems. Much of the work in this field is related to the original ideas developed by C. A. Petri. These graph models are today generally known as Petri Nets (PNs).

Modeling the software architecture of a prototype parallel machine

A high-level Petri net model of the software architecture of an experimental MIMD multiprocessor system for Artificial Intelligence applications is derived by direct translation of the code corresponding to the assumed workload. Hardware architectural constraints are then easily added, and formal reduction rules are used to simplify the model, which is then further approximated to obtain a performance model of the system based on generalized stochastic Petri nets. From the latter model it is possible to estimate the optimal multiprogramming level of each processor so as to achieve the maximum performance in terms of overall throughput (number of tasks completed per unit time).

Multi-microprocessor systems for real-time applications

1. Multiprocessor System Architecture.- 1.1 Distributed Processing and Multiprocessors.- 1.1.1 Classification Criteria.- 1.1.2 Computer Networks.- 1.1.3 Multiple Processor Systems.- 1.1.4 Special Purpose Machines.- 1.1.5 Other Classifications of Distributed Systems.- 1.2 Multiprocessor Systems.- 1.2.1 Multiprocessor Structures.- 1.2.2 The Interconnection Network.- 1.2.3 Shared Bus.- 1.2.4 Multiport Memory.- 1.2.5 Crossbar Switches.- 1.2.6 Multistage Interconnection Networks.- 1.2.7 Applications of Multiple Processors.- 1.3 Description Techniques for Multiprocessors.- 1.3.1 Levels of Description.- 1.3.2 Selection of the Description Level.- 1.3.3 The PMS Notation.- 1.3.4 The MSBI Notation.- 1.4 Some Multiprocessor Systems.- 1.4.1 Selection Criteria.- 1.4.2 The Cm*.- 1.4.3 The C.mmp.- 1.4.4 The PLURIBUS.- 1.4.5 The ?* System.- 1.4.6 The iAPX432 System.- 1.4.7 The TOMP Multiprocessor System.- 1.5 References.- 2. Performance Analysis of Multiprocessor Systems.- 2.1 Performance Evaluation of Bus Oriented Multiprocessor Systems.- 2.1.1 Introduction.- 2.1.2 Modeling Assumptions.- 2.1.3 The System Workload.- 2.1.4 Architecture 1.- 2.1.5 Architecture 2.- 2.1.6 Architecture 3.- 2.1.7 Architecture 4.- 2.1.8 Architecture Comparison.- 2.1.9 Choice of the Architecure of TOMP.- 2.2 Other Modeling Techniques and Measurements.- 2.2.1 Introduction.- 2.2.2 Stochastic Petri Net Models.- 2.2.3 Queueing Network Models.- 2.2.4 Measurements.- 2.3 References.- 3. TOMP Software.- 3.1 Introduction.- 3.1.1 Goals and Motivations.- 3.1.2 Limits.- 3.1.3 Overall System Description.- 3.2 Interprocess Communication.- 3.2.1 Model and Primitive Operations.- 3.2.2 Low Level Communication Protocol.- 3.3 The Executive.- 3.3.1 System Initialization.- 3.3.2 Process Management.- 3.3.3 Interrupt Handling.- 3.3.4 Monitoring Functions.- 3.4 Monitoring and Debug.- 3.4.1 General Architecture.- 3.4.2 Debugging Functions.- 3.5 Utilities.- 3.5.1 Terminal Handler.- 3.5.2 File System.- 3.5.3 Common Memory Allocator.- 3.6 System Generation.- 3.7 A Critical Review.- 3.8 References.- 4. Design of Multiprocessor Buses.- 4.1 Introduction.- 4.2 Basic Protocols.- 4.2.1 Elementary Operations.- 4.2.2 Types of Information Transfer Cycles.- 4.2.3 Synchronization of the Action Flow.- 4.3 Bused Systems.- 4.3.1 Channel Allocation Techniques.- 4.3.2 Bus Arbitration.- 4.3.3 The Distributed Self-selection Arbiter.- 4.4 Electrical Behaviour of Backplane Lines.- 4.4.1 Definition of Signal Levels.- 4.4.2 Transmission Line Effects.- 4.4.3 Crosstalk.- 4.4.4 Protocol Speed.- 4.5 Protocol Extension.- 4.5.1 The Enable/Disable Technique.- 4.5.2 Bus Supervisors.- 4.6 References.- 5. Some Examples of Multiprocessor Buses.- 5.1 Introduction.- 5.2 The Multibus Backplane.- 5.2.1 History and Main Features.- 5.2.2 Physical and Electrical Specifications.- 5.2.3 The Information Transfer Protocol.- 5.2.4 Special Features.- 5.2.5 Timing and Pinout.- 5.3 The VME Backplane Bus.- 5.3.1 History and Main Features.- 5.3.2 Physical and Electrical Specifications.- 5.3.3 The Information Transfer Protocol.- 5.3.4 Special Features.- 5.4 The 896 Backplane Bus.- 5.4.1 History and Main Features.- 5.4.2 Physical and Electrical Specifications.- 5.4.3 The Information Transfer Protocol.- 5.4.4 Special Features.- 5.4.5 Timing and Pinout.- 5.5 The M3BUS Backplane.- 5.5.1 History and Main Features.- 5.5.2 Physical and Electrical Specifications.- 5.5.3 System Organization and Control.- 5.5.4 The Arbitration Protocol.- 5.5.5 The Addressing Protocol.- 5.5.6 The Data Transfer Protocol.- 5.5.7 Interrupt and Interprocessor Communication.- 5.5.8 Supervisor Protocol.- 5.5.9 The Serial Bus.- 5.5.10 Timing and Pinout.- 5.6 References.- 6. Hardware Modules for Multiprocessor Systems.- 6.1 Introduction.- 6.2 System Design.- 6.2.1 Physical Organization of Multiprocessor Systems.- 6.2.2 Board Design Guidelines.- 6.3 Slave Modules.- 6.3.1 Organization of Slave Modules.- 6.3.2 Address Decoders and Latches.- 6.3.3 Slave Control Logic.- 6.3.4 Slave Buffering.- 6.4 Master Modules.- 6.4.1 Organization of Master Modules.- 6.4.2 External Access Decoder and Bus Arbitration.- 6.4.3 Master Control Logic.- 6.4.4 Master Buffering.- 6.5 Interrupt Structures.- 6.5.1 Requirements for Multiprocessor Systems.- 6.5.2 System Controls.- 6.5.3 Processor Interrupts.- 6.5.4 Centralized Interrupt Handler.- 6.5.5 Distributed Interrupt Handler.- 6.5.6 Serial Lines.- 6.6 Special Modules.- 6.6.1 Multiple-slave Modules.- 6.6.2 Bus Windows.- 6.6.3 Dual-port Slaves.- 6.6.4 Master-slave Modules.- 6.6.5 Block Transfer Units.- 6.6.6 Supervisor Modules.- 6.7 References.- 7. Multiprocessor Benchmarks.- 7.1 Introduction.- 7.2 The Concept of Performance.- 7.3 Parallel Programming.- 7.4 Parallel Notation Form.- 7.5 Parallel Sorting Techniques.- 7.6 Measurements and Analysis of Results.- 7.7 Conclusion.- 7.8 References.

The μ Project: An Experience with a Multimicroprocessor System

Which processor interconnection method makes a modular, reconfigurable system perform best in a given application? Certain tools and strategies help provide the answer.

PERFORMANCE ANALYSIS OF MULTIPROCESSOR SYSTEMS

This chapter describes a multiprocessor performance evaluation case study, and the modeling tools that were developed for this purpose. It is shown how the choice of the architecture of a multiprocessor system can be guided by analytical performance predictions in conjunction with implementation issues. The goal of the project of a multiprocessor system is the development of an efficient architecture which should not experience bottlenecks at the physical level due to contention for shared resources. A description is given of how the comparison among candidate architectures must be done using common assumptions and a similar workload model. Only after this preliminary work can an architecture be chosen and implemented as a good compromise between performance and implementation costs.

A Microprocessor Integrated Laboratory

This note describes the response of an education system (the Istituto di Elettronica e Telecomunicazioni of the Politecnico di Torino) to the advent of the microprocessor. A long-term project to fulfill new requirements is described. This project is comprised of teaching methodologies, a research and educational laboratory, and a set of asociated activities that are extensively described in the note.

Microprocessors in a university electronic laboratory

Abstract An experience of a university laboratory of applied electronics in μprocessor field is described. A modular system allows student familiarization with μprocessor both in hardware and software. Problems encountered and solutions adopted are briefly outlined.

MIL project: a microcomputer integrated laboratory

Abstract The introduction of microprocessors has meant a tremendous change in electronic technology and it is a common feeling that, with the continuous improvement of LSI and VLSI technology, the future will evolve at least at the same rate. This revolution produced great changes not only in electronic products themselves, but deeply affected research laboratories, production plants and maintenance services of all industries manufacturing electronic equipment or incorporating electronics in their final products. The main effect was a great demand for people with knowledge coming from different and previously separated fields: computer science, software engineering and digital electronic design. The first answer to the need of a quick updating for designers came from the market itself and everyone knows how many one-day courses were offered on ‘everything you must know about microprocessors’. A more long-term answer is the responsibility of the universities and of the technical schools that must prepare the new people for the new technological wave.