G. Deptuch

Development of monolithic active pixel sensors for charged particle tracking

Monolithic active pixel sensors introduce a detection technique, where the active detecting element is a thin, moderately doped, and undepleted silicon layer and the readout electronics is implanted on top of it. The built-in potential, resulting from differences in doping, screens both parts, as well as it confines the charge diffusing to the readout electrodes. The R&D was triggered by the increasing need of high performance flavour identification capabilities that should be provided by future vertex detectors. The viability of the technology and its high tracking performances were demonstrated with small-scale prototypes, made of small arrays of a few thousands of pixels and more recently with a first prototype of a serviceable size of one million pixels. This paper summarizes results from tests performed with relativistic charged particles on prototypes essentially fabricated with a classical 3-transistor pixel configuration. Within the last year, two novel ideas optimising the pixel design for a vertex detector have been developed. They are presented with test results assessing their suitability.

Vertically Integrated Circuits at Fermilab

The exploration of vertically integrated circuits, also commonly known as 3D-IC technology, for applications in radiation detection started at Fermilab in 2006. This paper examines the opportunities that vertical integration offers by looking at various 3D designs that have been completed by Fermilab. The emphasis is on opportunities that are presented by through silicon vias (TSV), wafer and circuit thinning, and finally fusion bonding techniques to replace conventional bump bonding. Early work by Fermilab has led to an international consortium for the development of 3D-IC circuits for High Energy Physics. For the first time, Fermilab has organized a 3D MPW run, to which more than 25 different designs have been submitted by the consortium.

CMOS monolithic active pixel sensors for minimum ionizing particle tracking using non-epitaxial silicon substrate

Nonepitaxial, high resistivity silicon has been used as a substrate for implementation of CMOS monolithic active pixel sensors (MAPS) designed for high precision minimum ionizing particle tracking. The readout electronics circuitry is integrated directly on top of such a substrate using a standard commercial CMOS process. In this paper, measurements of these devices using a high-energy particle beam are presented. Efficient and performing MIP tracking is demonstrated for both small (20 /spl mu/m) and large (40 /spl mu/m) pixel readout pitch. Radiation hardness that satisfies many future particle physics applications is also proven. These results show that the use of epitaxial substrate for MAPS fabrication is not mandatory, opening a much larger choice of possible CMOS processes in the future.

Performance of a Fast Binary Readout CMOS Active Pixel Sensor Chip Designed for Charged Particle Detection

We report on the performance of the MIMOSA8 (HiMAPS1) chip. The chip is a 128times32 pixels array where 24 columns have discriminated binary outputs and eight columns analog test outputs. Offset correction techniques are used extensively in this chip to overcome process related mismatches. The array is divided in four blocks of pixels with different conversion factors and is controlled by a serially programmable sequencer. MIMOSA8 is a representative of the CMOS sensors development option considered as a promising candidate for the Vertex Detector of the future International Linear Collider (ILC). The readout technique, implemented on the chip, combines high spatial resolution capabilities with high processing readout speed. Data acquisition, providing control of the chip and signal buffering and linked to a VME system, was made on the eight analog outputs. Analog data, without and with a 55Fe X-ray source, were acquired and processed using off-line analysis software. From the reconstruction of pixel clusters, built around a central pixel, we deduce that the charge spread is limited to the closest 25 pixels and almost all the available charge is collected. The position of the total charge collection peak (and subsequently the charge-to-voltage conversion factor) stays unaffected when the clock frequency is increased even up to 150 MHz (13.6 mus readout time per frame). The discriminators, placed in the readout chain, have proved to be fully functional. Beam tests have been made with high energy electrons at DESY (Germany) to study detection efficiency. The results prove that MIMOSA8 is the first and fastest successful monolithic active pixel sensor with on-chip signal discrimination for detection of MIPs

A fast monolithic active pixel sensor with pixel-level reset noise suppression and binary outputs for charged particle detection

In order to develop precision vertex detectors for the future linear collider, fast monolithic active pixel sensors are studied. A standard CMOS 0.25 mum digital process is used to design a test chip which includes different pixel types, column-level discriminators, and a fully programmable digital sequencer. In-pixel amplification is implemented together with double sampling. Different charge-to-voltage conversion factors were obtained using amplifiers with different gains or diode sizes. Pixel architectures with dc and ac coupling to charge sensing element were proposed. Hits from conversion of 55Fe photons were recorded for the dc-coupled and ac-coupled pixel versions. Double sampling is functional and allows almost a complete cancellation of fixed pattern noise

Monolithic active pixel sensors with on-pixel amplification and double sampling operation

Abstract Monolithic Active Pixel Sensors (MAPS) constitute a novel technique for silicon position-sensitive detectors. Their development is driven by highly demanding performances of the vertex detector foreseen at the future linear collider. This paper presents a new approach for a detector based on the MAPS principle. The pixel concept proposed is foreseen to match with signal discrimination implemented on the chip. It combines on-pixel signal amplification with double sampling operation, and provides a signal resulting from the difference between the charges collected in two consecutive time slots. The device can be fabricated in a cheap standard CMOS process, using a wafer made of a moderately doped medium. The new pixel design uses only NMOS transistors, nwell/psub and pdiff/nwell diodes and poly1-to-poly2 capacitors. It is based on a principle of switched operation circuits with 15 transistor switches close to the minimum size and 14 transistors used for the signal amplification.

Test results of monolithic active pixel sensors for charged particle tracking

Abstract A new generation of semi-conducting pixel sensors for detecting minimum ionising particles (m.i.p.) was designed and first prototypes of Monolithic Active Pixel Sensors (MAPS), called MIMOSA, 2 were fabricated in a standard CMOS technology. The performances of the first prototypes were evaluated with high energy π− beams and with an X-ray source in strong magnetic fields. The beam test results demonstrate that the sensors detect m.i.p.s with very high efficiency and signal-to-noise ratio and provide excellent spatial resolution. The influence of strong magnetic fields is observed to be modest.

Silicon ultra fast cameras for electron and γ sources in medical applications

Abstract SUCIMA (Silicon Ultra fast Cameras for electron and γ sources In Medical Applications) is a project approved by the European Commission with the primary goal of developing a real time dosimeter based on direct detection in a Silicon substrate. The main applications, the detector characteristics and technologies and the data acquisition system are described.

Design and Tests of the Vertically Integrated Photon Imaging Chip

The Vertically Integrated Photon Imaging Chip (VIPIC) project explores opportunities of the three-dimensional integration for imaging of X-rays. The design details of the VIPIC1 chip are presented and are followed by results of testing of the chip. The VIPIC1 chip was designed in a 130 nm process, in which through silicon vias are embedded right after the front-end-of-line processing. The integration of tiers is achieved by the Cu-Cu thermo-compression or Cu-based oxide-oxide bonding. The VIPIC1 readout integrated circuit was designed for high timing resolution, pixel based, X-ray Photon Correlation Spectroscopy experiments typically using 8 keV X-rays at a synchrotron radiation facility. The design was done for bonding a Silicon pixel detector, however other materials can be serviced as long as the positive polarity of charge currents is respected.

The RatCAP front-end ASIC

We report on the design and characterization of a new ASIC for the RatCAP, a head-mounted miniature PET scanner intended for neurological and behavioral studies of an awake rat. The ASIC is composed of 32 channels, each consisting of a charge sensitive preamplifier, a 5-bit programmable gain in the pole-zero network, a 3rd order bipolar semi-Gaussian shaper (peaking time of 80 ns), and a timing and energy discriminator. The energy discriminator in each channel is used to arm the zero-crossing discriminator and can be programmed to use either a low energy threshold or an energy gating window. A 32-to-1 serial encoder is embedded to multiplex into a single output the timing information and channel address of every event. Finally, LVDS I/O were integrated on chip to minimize the digital noise on the read-out PCB. The ASIC was realized in the TSMC 0.18 mum technology, has a size of 3.3 mm times 4.5 mm and a power consumption of 117 mW. The gate length of the N-channel MOSFET input device of the charge sensitive preamplifier was increased to minimize 1/f noise. This led to a factor 1.5 improvement of the ENC with respect to the first version of the ASIC. An ENC of 650 e-rms was measured with the APD biased at the input. In order to predict the achievable timing resolution, a model was derived to estimate the photon noise contribution to the timing resolution. Measurements were performed to validate the model, which agreed within 12%. The coincidence timing resolution between two typical LSO-APD-ASIC modules was measured using a 68Ge source. Applying a threshold at 420 keV, a timing resolution of 6.7 ns FWHM was measured. An energy resolution of 18.7% FWHM at 511 keV was measured for a 68Ge source.