G.E. Taylor

Testing mixed signal ASICs through the use of supply current monitoring

The authors investigate testing of mixed signal integrated circuits. Several approaches are proposed, most requiring careful partitioning of the analogue and digital sections. However, the use of supply current monitoring is applicable to both digital and analogue sections. Digital testing has been widely investigated, concentrating on quiescent I/sub ddq/ testing. Using pseudo-random binary test signals with supply current testing, high fault coverage of both catastrophic FET faults and gate oxide shorts in the analogue section is shown to be obtainable. Use of on-chip supply sensors has also been investigated.<<ETX>>

Can supply current monitoring be applied to the testing of analogue as well as digital portions of mixed ASICs

Investigations are made into the suitability of supply current monitoring as a technique for the testing of analogue circuit modules. Iddq monitoring is already recognised in the digital field. The possibility of a unified testing approach for mixed ASICs is raised. The potential effectiveness of the method is investigated. Simulation results are reported to illustrate typical supply current levels for nominal and defective circuits. Analogue fault detection by this technique is compared with detection by observation of the circuits output.<<ETX>>

Fault orientated test and fault simulation of mixed signal integrated circuits

This paper considers the implications of structural test for analog and mixed signal (analog and digital) circuits and describes fault simulation software suitable for investigating a variety of test methods. Results from simulation investigations of dynamic supply current test are presented and compared with results obtained for real circuits. In both cases the results indicate increased fault coverage and reliability benefits. The dynamic supply current monitoring equipment used to implement the hardware test is described.

Logic value assignment contribution to testability analysis

Due to the increased complexity of the devices produced, test generation has become one of the more important cost factors in VLSI production. Testability measures are one attempt to reduce the test cost. There are a number of techniques adopted for the evaluation of such testability measures. Most of these are based on controllability and observability concepts. The basic idea is to associate a quantitive measure with each node in the circuit under analysis. The approach proposed in this paper operates as follows: 1) Consider the relationship among objects and evaluate testability costs accordingly; 2) Use both static and dynamic measures. Only one pass through the circuit is required. This method is more deterministic than other techniques and allows hierarchical implementation (including high level primitives).<<ETX>>

Mixed signal test considerations for switched current signal processing

Single devices including both analog and digital functions are now a practical possibility, but testing remains a problem and a bar to widespread use. Possible approaches to design using current monitoring are reviewed. The implications of these approaches for switched current devices are investigated, with emphasis on current monitoring. Simulation results show that high levels of fault coverage are possible using current monitoring. Natural processing of current mode signals in a discrete time environment lends itself to the possibility of on-chip reconfigurable self-test and test pattern generation.<<ETX>>

Testability of digital circuits via the spectral domain

The authors demonstrate how the spectral testability of digital circuits can be evaluated in the spectral domain using two standard testability measures: controllability and observability. It is shown how these measures are obtained. Software considerations are discussed, and the evaluation of the testability of an SN74181 arithmetic logic chip is given as an example.<<ETX>>