G. Seetharaman

Design of Low Power TPG Using LP-LFSR

This paper presents a novel test pattern generator which is more suitable for built in self test (BIST) structures used for testing of VLSI circuits. The objective of the BIST is to reduce power dissipation without affecting the fault coverage. The proposed test pattern generator reduces the switching activity among the test patterns at the most. In this approach, the single input change patterns generated by a counter and a gray code generator are Exclusive -- ORed with the seed generated by the low power linear feedback shift register [LP-LFSR]. The proposed scheme is evaluated by using, a synchronous pipelined 4×4 and 8×8 Braun array multipliers. The System-On-Chip (SOC) approach is adopted for implementation on Altera Field Programmable Gate Arrays (FPGAs) based SOC kits with Nios II soft-core processor. From the implementation results, it is verified that the testing power for the proposed method is reduced by a significant percentage.

Design and FPGA Implementation of Self Tuned Wavepipelined Filters

In this paper, a novel scheme is proposed for FPGA implementation of a wavepipelined filter using Distributed Arithmetic Algorithm (DAA). To make the circuit independent of fabrication variations in the parameters, a sub-optimal wavepipelined scheme is proposed for the various combinational blocks of the DA filter. A self tuning FSM is in-built to choose the clock skew and clock period for I/O registers between the wavepipelined blocks. To test the efficacy of the scheme proposed, three filters with 4, 8 and 10 taps respectively are implemented using DAA approach on Xilinx Spartan II XC2S100-5PQ208 device. The filters are implemented using three schemes: synchronous pipelining, sub-optimal wavepipelining and no pipelining (i.e., using neither synchronous pipelining nor wavepipelining). From the implementation results, it is observed that wavepipelined DA filters are faster by a factor of 1.31–1.61 compared to non-pipelined DA filters. The synchronous pipelined DA filters are in turn faster by a factor of 1.73-2.06 compared to the wavepipelined DA filters. The increased speeds are achieved by increasing the number of slices by 25%-33%, the number of registers by 350-530% and power dissipation by 107-167%. The delay-register product of the wavepipelined DA filters are reduced by a factor of 2.64-3.06 compared to the pipelined DA filters. The technique proposed in this paper is also applicable for ASICs and FPGAs from other vendors.

Multi bit random and burst error correction code with crosstalk avoidance for reliable on chip interconnection links

Abstract We propose an energy efficient error control code for the on chip interconnection link capable of correcting any type of error patterns including random and burst errors up to five (i.e. 1, 2, 3, 4, and 5 errors). The proposed code is based on single error correction–double error detection (SEC–DED) extended Hamming code and standard triplication error correction scheme. Using single error correction–double error detection (SEC–DED) extended Hamming code and standard triplication error correction scheme a new decoding algorithm is proposed to correct multiple errors up to five in on-chip interconnection link. Triplication error correction scheme provides crosstalk avoidance by reducing the coupling capacitance of the interconnection wire. The proposed code provides high reliability compared to other error control codes. The performance of the proposed code is evaluated for codec area, codec power, codec delay, residual flit error rate, link swing voltage and link power. For the given reliability requirement of 10−5 and 10−20, the proposed code achieves low residual flit error rate and low swing voltage. The low swing voltage results in the reduction of the link power consumption up to 68% compared to the existing error control codes for on chip interconnection link. The low residual flit error rate and low link power make the proposed code appropriate for on chip interconnection link.

A Modified Algorithm for Removal of Salt and Pepper Noise in Color Images

In this paper a modified simple edge preserved denoising algorithm to remove salt and pepper noise in digital color images is presented. The algorithm has three steps: noisy pixel detection, replacement of noisy pixels, confirmation by comparing with a threshold. In addition a median filtering is added to improve the quality of the image. The proposed algorithm prevents the smoothing of edges in the noise removal process, by predicting the possible edges and taking the mean value from the predicted edge. In the proposed algorithm the computational complexity is less with maximum edge preservation. The color images are denoised by extracting the R, G and B planes from the noisy image, denoised separately and are merged together to form the color image, rather than converting to gray for denoising and then reconstructing from the denoised gray image. The algorithm is implemented partially in MATLAB and MODELSIM. Experimental results show that the proposed algorithm yields visually pleasing images in terms of qualitative and quantitative evaluation compared to other standard algorithms.

Hamming Product Code Based Multiple Bit Error Correction Coding Scheme Using Keyboard Scan Based Decoding for on Chip Interconnects Links

In this paper, we present multiple bit error correction coding scheme using extended Hamming product code combined with type II HARQ and keyboard scan based error flipping to correct multiple bit errors for on chip interconnect. The keyboard scan based error flipping reduces the hardware complexity of the decoder compared to the existing three stages iterative decoding method for on chip interconnects. The proposed method of decoding achieves 86% of reduction in area and 23% of reduction in decoder delay with only small increase in residual flit error rate compared to the existing three stage iterative decoding scheme for multiple bit error correction. The proposed code also achieves excellent improvement in residual flit error rate and up to 66% of links power consumption compared to the other error control schemes. The low complexity and excellent residual flit error rate make the proposed code suitable for on chip interconnection links.

Automation Schemes for FPGA Implementation of Wave-Pipelined Circuits

Operating frequencies of combinational logic circuits can be increased using Wave-Pipelining (WP), by adjusting the clock periods and clock skews. In this article, Built-In Self-Test (BIST) and System-on-Chip (SOC) approaches are proposed for automating this adjustment and they are evaluated by implementation of filters using a Distributed Arithmetic Algorithm (DAA) and sinewave generator using the COordinate Rotation DIgital Computer (CORDIC). Both the circuits are studied by adopting three schemes: wave-pipelining, pipelining, and nonpipelining. Xilinx Spartan II and Altera Cyclone II FPGAs with Nios II soft-core processor are used for implementation of the circuits with the BIST and SOC approaches, respectively. The proposed schemes increase the speed of the WP circuits by a factor of 1.19--2.6 compared to nonpipelined circuits. The pipelined circuits achieve higher speed than the WP circuits by a factor of 1.13--3.27 at the cost of increase in area and power. When both pipelined and WP circuits are operated at the same frequency, the former dissipates more power for circuits with higher word sizes and for moderate logic depths. The observation regarding the dependence of the superiority of the WP circuits with regard to power dissipation on the logic depth is one of the major contributions of this article.

Automation techniques for implementation of hybrid wave-pipelined 2D DWT

In the literature, techniques such as pipelining and wave-pipelining (WP) are proposed for increasing the operating frequency of a digital circuit. In general, use of pipelining results in higher speed at the cost of increase in the area and clock routing complexity. On the other hand, use of WP results in less clock routing complexity and less area but enables the digital circuit to be operated only at moderate speeds. In this paper, a hybrid wave-pipelining scheme is proposed to get the benefits of both pipelining and WP techniques. Major contributions of this paper are: proposal for the implementation of 2D DWT using lifting scheme by adopting the hybrid wave-pipelining and proposal for the automation of the choice of clock frequency and clock skew between the input and output registers of wave-pipelined circuit using built in self test (BIST) and system-on-chip (SOC) approaches. In the hybrid scheme, different lifting blocks are interconnected using pipelining registers and the individual blocks are implemented using WP. For the purpose of evaluating the superiority of the schemes proposed in this paper, the system for the computation of one level 2D DWT is implemented using the following techniques: pipelining, non-pipelining and hybrid wave-pipelining. The BIST approach is used for the implementation on Xilinx Spartan-II device. The SOC approach is adopted for implementation on Altera and Xilinx field programmable gate arrays (FPGAs) based SOC kits with Nios II or Micro blaze soft-core processors. From the implementation results, it is verified that the hybrid WP circuit is faster than non-pipelined circuit by a factor of 1.25–1.39. The pipelined circuit is in turn faster than the hybrid wave-pipelined circuit by a factor of 1.15–1.38 and this is achieved with the increase in the number of registers by a factor of 1.79–3.15 and increase in the number of LEs by a factor of 1.11–1.65. The soft-core processor based automation scheme has considerably reduced the effort required for the design and testing of the hybrid wave-pipelined circuit. The techniques proposed in this paper, are also applicable for ASICs. The optimization schemes proposed in this paper are also applicable for the computation of other image transforms such as DCT, DHT.

SOC implementation of wave-pipelined circuits

In the literature, wave-pipelining is proposed as one of the techniques for increasing the operating frequency of the digital circuits. Higher operating frequencies can be achieved in wave-pipelined (WP) circuits, by adjusting the clock periods and clock skews so as to latch the outputs of combinational logic circuits at the stable periods. Major contributions of this paper are the proposal for the use of soft-core processor for the automation of the above tasks, and the superiority of the WP circuits with regard to power dissipation. The proposed scheme is evaluated by using two circuits: filters using distributed arithmetic algorithm (DAA) and a sine wave generator using coordinate rotation digital computer (CORDIC) algorithm. Both the circuits are studied by adopting three different schemes: wave-pipelining, pipelining and non-pipelining. The system-on-chip (SOC) approach is adopted for implementation on Altera field programmable gate arrays (FPGAs) based SOC kits with Nios II soft-core processor. From the implementation results, it is verified that the WP circuits are faster compared to non-pipelined circuits. The pipelined circuits are found to be faster than the WP circuits and this is achieved at the cost of increase in area and power. For the power dissipation, when both pipelined and WP circuits are operated at the same frequency, the former dissipates more power for circuits with higher word sizes and for medium taps filters. From the implementation results, it is verified that the superiority of the power dissipation of the WP circuits depends not only on the area but also on the logic depth of the circuit. This observation is made for the first time for the WP circuits.

VLSI implementation of hybrid wave-pipelined 2D DWT using lifting scheme

A novel approach is proposed in this paper for the implementation of 2D DWT using hybrid wave-pipelining (WP). A digital circuit may be operated at a higher frequency by using either pipelining or WP. Pipelining requires additional registers and it results in more area, power dissipation and clock routing complexity. Wave-pipelining does not have any of these disadvantages but requires complex trial and error procedure for tuning the clock period and clock skew between input and output registers. In this paper, a hybrid scheme is proposed to get the benefits of both pipelining and WP techniques. In this paper, two automation schemes are proposed for the implementation of 2D DWT using hybrid WP on both Xilinx, San Jose, CA, USA and Altera FPGAs. In the first scheme, Built-in self-test (BIST) approach is used to choose the clock skew and clock period for I/O registers between the wave-pipelined blocks. In the second approach, an on-chip soft-core processor is used to choose the clock skew and clock period. The results for the hybrid WP are compared with nonpipelined and pipelined approaches. From the implementation results, the hybrid WP scheme requires the same area but faster than the nonpipelined scheme by a factor of 1.25-1.39. The pipelined scheme is faster than the hybrid scheme by a factor of 1.15-1.39 at the cost of an increase in the number of registers by a factor of 1.78-2.73, increase in the number of LEs by a factor of 1.11-1.32 and it increases the clock routing complexity.

Synthesis techniques for implementation of wave-pipelined circuits in ASICs

Higher operating frequencies may be obtained in digital systems by using wave-pipelining which permits clock frequencies higher that dictated by largest propagation delay between input and output. This, however, requires proper selection of clock periods and clock skews so as to latch the output of combinational logic circuits at the stable periods. In the literature, only trial and error and manual procedures are adopted for these selections. The major contribution of this paper is the proposal for three schemes for synthesis of wave-pipelined circuits using commercially available synthesis tools. To test the efficacy of the proposed schemes, an 8-bit ripple carry is implemented by adopting three schemes: wave-pipelining, pipelining and non-pipelining. From the implementation results, it is observed that the wave pipelined circuit is 2.8 times faster than the non pipelined circuit at the cost of increase in area by a factor of 1.8. The wave pipelined circuit 3.5% faster compared to pipelined circuit and requires 8.7% less area over pipelined circuit.