B. Venkataramani

FPGA Implementation of Support Vector Machine Based Isolated Digit Recognition System

In this paper, two schemes for FPGA implementation of multi-class SVM based isolated digit recognition system are proposed, one using only logic elements and another using both soft-core processor and logic elements(LEs). One of the major contributions of this paper is the proposal for implementation of the decision function using only fixed point arithmetic without compromising the recognition accuracy. Compared to the scheme which uses floating point arithmetic, the proposed scheme reduces the number of LEs required by a factor of 3.29. The second scheme proposed results in about 25 times lower area compared to the first scheme. For the soft-core processor approach, a custom instruction is proposed for floating point arithmetic. Speaker dependent TI46 database of isolated digits is used for training and testing. Features are extracted using both Linear Predictive Coefficients (LPC) and Mel Frequency Cepstral Coefficients(MFCC) and features are compressed using Self Organized Feature Mapping (SOFM). This in turn is used by the SVM classifier to evaluate the recognition accuracy and the hardware resources utilized. Both the schemes proposed result in 100% recognition accuracy when implemented on Altera Cyclone II FPGA. The proposed schemes can also be used for speaker verification and speaker authentication applications. Since the scheme which uses soft-core processor requires lower area, it can be used for systems which require a large vocabulary size.

Performance Evaluation of Adhoc Networks with Different Multicast Routing Protocols and Mobility Models

A mobile ad hoc network (MANET) is a network consisting of a set of wireless mobile nodes that communicate with each other without centralized control or established infrastructure. The mobility model should represent the realistic behavior of each mobile node in the MANET. Routing protocols for ad hoc networks are typically evaluated using simulation, since the deployment of ad hoc networks is still relatively rare. However, past evaluations of multicast routing protocols have utilized a single, simple Random way point mobility model, and thus do not capture the variety of mobility patterns likely to be exhibited by ad hoc applications. In this paper, the results on the simulation study of the impact of different mobility models on Multicast Routing Protocols are presented. The performance of On Demand multicast Routing Protocol (ODMRP) and Adhoc demand Driven Multicast Routing(ADMR) protocol under different mobility scenario is evaluated. The results show that the throughput of ADMR is higher than of ODMRP at high mobility. This is achieved at the cost of increase in delay and transmission over head. Under low mobility, ODMRP has higher throughput than AMDR. Among the three mobility models considered, the throughput of ODMRP is the highest at low mobility. The results show that the protocols performances vary widely across the different mobility models.

Hardware Implementation of Real-Time Speech Recognition System Using TMS320C6713 DSP

Continuous, real-time speech recognition is required for various mobile and hands-free applications. In this paper, hardware implementation of real-time speech recognition system is proposed using two approaches and their performances are evaluated. The first approach uses Mel Filter Banks with Mel Frequency Cepstrum Coefficients (MFCC) as feature input and the second approach uses Cochlear Filter Banks with Zero-crossings (ZC) as feature input for recognition. The features extracted from input speech are fed to multi-class Support Vector Machine (SVM) classifier for recognition. The proposed recognition systems are implemented on a Texas Instruments TMS320C6713 floating point digital signal processor for recognizing isolated digits (0-9) and their performances are compared. It is observed that the program memory required for MFCC feature extraction is 44.42% higher than that required for feature extraction using Cochlear filters. Recognition accuracies of 93.33% and 98.67% are achieved for feature inputs from Mel filter banks and Cochlear filter banks respectively. It is also observed that the computational complexity of feature extraction using cochlear filters is 1.53 times of that required for MFCC feature extraction. The recognition performance is also studied for different combinations of test and training utterances. It is found that training using 15 utterances of each digit results in best recognition accuracy. The techniques proposed here can be adapted for various other hands-free consumer applications such as washing machines, hands-free cordless and many more.

Evaluation of Edge Detection Techniques towards Implementation of Automatic Target Recognition

The vision of Automatic Target Recognition (ATR) is through an integrated command identification architecture that combines non-cooperative and cooperative identification sensors and systems. The ATR implemented shall support development of situational awareness i.e., overall, general knowledge of the tactical battlefield environment, including the location of friendly, neutral, and enemy forces and plan of action for battle. The required operational capability will then be achieved by combining onboard data from multiple sensors and systems with indirectly supplied off board information. Edge Detection is one of the major image-processing requirements for achieving efficient and accurate target recognition in difficult domains. The on-board sensors used on combat aircraft are Electro-optic Targeting Sensors (EOTS), Infra-red (IR) sensors, Radar, Synthetic Aperture Radar (SAR) and Inverse SAR (ISAR) providing vast amount of images with different characteristics helpful for detecting targets. This paper concentrates on the assessment of advanced edge detection techniques on all types of sensor input images obtained for the implementation of automatic target recognition for air-to-air, air-to-sea and air-to-ground applications. This paper also describes the approach towards implementation of automatic target recognition for the entire range of sensor inputs. The proposed algorithm for automatic target recognition is for implementation on airborne systems with potential use on ground stations.

Design of a modified one-against-all SVM classifier

Support Vector Machine (SVM) is one of the state of-the-art tools for linear and nonlinear pattern classification. One of the design issues in SVM classifier is reducing the number of support vectors without compromising the classification accuracy. In this paper, a novel technique which requires only a subset of the support vectors is proposed. The subset is obtained by including only those support vectors for which Lagrange multiplier is greater than a threshold. In order to find the subset which yields the highest classification accuracy with the least number of support vectors in the subset, the recognition performance corresponding to subsets with different threshold values are to be evaluated and compared. The proposed technique is applied for SVM based isolated digit recognition system and is studied using speaker dependent as well as multispeaker dependent TI46 database of isolated digits. Two feature extraction techniques, one using LPC and another using MFCC are applied to the speech from the above database and the features are mapped using SOFM. This in turn is used by the SVM classifier to evaluate the recognition accuracy. The proposed technique is applied to One-Against-All (OAA) scheme and is denoted as Modified One-Against-All (M-OAA) approach in this paper. Based on this study, it is found that for MFCC feature input, the proposed M-OAA based SVM classifier approach results in reduction of support vectors by a factor of 1.86 to 18.3 with no compromise in recognition accuracy. For LPC feature input, the M-OAA based SVM classifier results in reduction of support vectors by a factor of 1.59 to 2.52 without any compromise in recognition accuracy for some cases and with a maximum of 1% degradation in recognition accuracy for some cases. The proposed approach is also applicable for other schemes such as Half-Against-Half (HAH) and Directed Acyclic Graphs (DAG) based SVM classifiers as well as for any other classification problem such as face recognition, fingerprint recognition, target recognition, speaker recognition and speaker verification.

Design and FPGA implementation of image block encoders with 2D-DWT

In this paper schemes for computation of 2D DWT of 32 /spl times/ 32 subimages using both lifting and DAA technique with Baugh-Wooley multiplier (BWM) is proposed and implemented on Xilinx XC2S150PQ208-5 FPGAs. The implementation results show that the lifting scheme with BWM requires about 20% less area but is 1.55 times faster than that using conventional 2s complement multiplier (C2M). For larger word sizes, the DAA with BWM is found to be 1.2 times faster than that using C2M. An overlap method for processing 128 /spl times/ 128 image using subimages of size 32 /spl times/ 32 is proposed and implemented. The 2D DWT of the image is also computed using a C program. The LL1 component of the image obtained using all the above schemes are found to be matching well with the original image. FPGA implementation of higher level 2D DWT is under progress.

FPGA implementation of isolated digit recognition system using modified back propagation algorithm

In this paper, the details of implementation of an isolated digit recognition system using NiosII soft-core processor are presented. Mel Frequency Cepstral Coefficients (MFCC) is used for feature extraction, multi layer perceptron (MLP) is used for classification and self organized feature map (SOFM) is employed for dimensionality reduction of features. Using TIDIGITS speech data base, various MLP architectures are studied and it is found that the recognition accuracy of 100% is obtained with the least computational complexity using single layer MLP with 10 hidden nodes. MLP is trained using both BP and modified BP algorithms and it is observed that MBP is 2.62 times faster than BP with 100% recognition accuracy. The digit recognition system is implemented on Altera CycloneII FPGA using hardware/software partitioning and the following observations are made: implementation of radix-4 FFT and remaining blocks for the calculation of MFCC using universal CORDIC processor as hardware/software partitioning is dasia10psila times faster compared to the complete software implementation on NiosII processor. The hardware accelerator for the NIOSII processor for implementation of MLP increases the recognition speed by a factor of 278. The technique proposed in this paper is also applicable for other soft-core processor such as Microblaze and Picoblaze.

A low power 700MSPS 4bit time interleaved SAR ADC in 0.18um CMOS

The design and implementation details of a 4-bit time interleaved Successive approximation register (SAR) analog to digital converter (ADC) for UWB application is presented in this paper. Low latency SAR ADC has been implemented by detecting two bits per clock cycle. Major contribution of this paper is that it uses only two capacitive DACs instead of three capacitive DACs. This is achieved by using Gilbert cell preamplifier in one of comparator detectors. It reduces the power consumption by approximately 33%. The ADC is implemented in 0.18μm CMOS technology and has total power consumption of 23.3mw at sampling frequency of 700MSPS for an input swing of 1V peak to peak. The proposed SAR ADC gives SNDR of 23.9dB, SFDR of 32.6dB and THD of −37.8dB at nyquist rate. The proposed ADC enables a larger input swing with Figure of Merit of 2.5 which is higher than that of SAR ADCs reported in the literature.

VLSI implementation of Gm-C filter using modified Nauta OTA with double CMOS pair

In the literature, a modified Nautas OTA has been proposed for achieving higher PSRR and CMRR. In this paper, a modified Nautas OTA with double CMOS pair is proposed and is used for implementing a programmable Gm-C filter. The double CMOS pair enables the transconductance to be varied by varying the bias voltages at high impedance nodes. This in turn results in programmability of the filter (F-tuning). For the purpose of comparison, the proposed OTA and Nautas OTA reported in the literature are implemented in UMC-0.18µm CMOS process and studied through simulation. The proposed OTA results in 11 dB increase in the PSRR and 21 dB increase in the CMRR compared to the Nautas OTA. The tunable second order Gm-C band pass filter using the proposed OTA is implemented and studied. Simulation of filter is done with BSIM3V3 parameters under (±0.9V) supply voltage and (±1.4V) supply voltage for biasing of double CMOS pair. It is verified from the post-layout simulation that the filter can be tuned over the range (10MHz–300MHz).

500MS/s 4-b time interleaved SAR ADC using novel DAC architecture

The design and implementation details of a 4-bit time interleaved Successive approximation register (SAR) analog to digital converter (ADC) for UWB application is presented in this paper. Major contribution of this paper is the proposal for a novel digital to analog converter (DAC) architecture which reduces the area required for capacitors by a factor of three, while the maximum error due mismatch between capacitors is reduced by 33% compared to the architecture reported in the literature. The ADC is implemented in .18µm CMOS technology and has total power consumption of 17.6mw at sampling frequency of 500MS/s for an input swing of 1V peak to peak. Proposed SAR ADC gives SNDR of 23.7dB, SFDR of 31.5dB and THD of −32.2dB at Nyquist rate. The proposed ADC enables the input swing to be increased by 25% while maintaining Figure of merit same compared to a SAR ADC reported in the literature.