Gabor Szedo

High-performance timing-driven rank filter

This paper presents an FPGA implementation of a high-performance rank filter for video and image processing. The architecture exploits the features of current FPGAs and offers tradeoffs between complexity and performance. By maximizing the operating frequency, the complexity of the filter structure can be considerably reduced compared to previous 2D architectures.

High Performance Timing-Driven Rank Filter

This paper presents an FPGA implementation of a high performance rank filter for video and image processing. The architecture exploits the features of current FPGAs and offers tradeoff between complexity and clock speed. By maximizing the operating frequency the complexity of the filter structure can be considerably reduced compared to previous 2D architectures.

Cost Effective 2×2 Inner Product Processors

Direct hardware realizations of digital filters on FPGA devices require efficient implementation of the multiplier modules. The distributed arithmetic form of the inner product processor array offers the possibility of merging the individual partial products, which leads to reduced logic complexity. Although this possibility can be exploited mainly in case of fixed coefficient multiplication and larger data set, for non-fixed, small sized, 2×2 arrays the integrated functional unit also results in significant achievements in area savings, especially in case of complex multiplication or Givens rotations in orthogonal filter structures. The proposed inner product processor uses the Canonical Signed Digit code for the representation of the multiplier operands.