Gabriel A. Rincón-Mora

Accurate electrical battery model capable of predicting runtime and I-V performance

Low power dissipation and maximum battery runtime are crucial in portable electronics. With accurate and efficient circuit and battery models in hand, circuit designers can predict and optimize battery runtime and circuit performance. In this paper, an accurate, intuitive, and comprehensive electrical battery model is proposed and implemented in a Cadence environment. This model accounts for all dynamic characteristics of the battery, from nonlinear open-circuit voltage, current-, temperature-, cycle number-, and storage time-dependent capacity to transient response. A simplified model neglecting the effects of self-discharge, cycle number, and temperature, which are nonconsequential in low-power Li-ion-supplied applications, is validated with experimental data on NiMH and polymer Li-ion batteries. Less than 0.4% runtime error and 30-mV maximum error voltage show that the proposed model predicts both the battery runtime and I-V performance accurately. The model can also be easily extended to other battery and power sourcing technologies.

A low-voltage, low quiescent current, low drop-out regulator

The demand for low-voltage, low drop-out (LDO) regulators is increasing because of the growing demand for portable electronics, i.e., cellular phones, pagers, laptops, etc. LDOs are used coherently with dc-dc converters as well as standalone parts. In power supply systems, they are typically cascaded onto switching regulators to suppress noise and provide a low noise output. The need for low voltage is innate to portable low power devices and corroborated by lower breakdown voltages resulting from reductions in feature size. Low quiescent current in a battery-operated system is an intrinsic performance parameter because it partially determines battery life. This paper discusses some techniques that enable the practical realizations of low quiescent current LDOs at low voltages and in existing technologies. The proposed circuit exploits the frequency response dependence on load-current to minimize quiescent current flow. Moreover, the output current capabilities of MOS power transistors are enhanced and drop-out voltages are decreased for a given device size. Other applications, like dc-dc converters, can also reap the benefits of these enhanced MOS devices. An LDO prototype incorporating the aforementioned techniques was fabricated. The circuit was operable down to input voltages of 1 V with a zero-load quiescent current flow of 23 /spl mu/A. Moreover, the regulator provided 18 and 50 mA of output current at input voltages of 1 and 1.2 V, respectively.

Designing 1-V op amps using standard digital CMOS technology

This paper addresses the difficulty of designing 1-V capable analog circuits in standard digital complementary metal-oxide-semiconductor (CMOS) technology, Design techniques for facilitating 1-V operation are discussed and 1-V analog building block circuits are presented. Most of these circuits use the bulk-driving technique to circumvent the metal-oxide-semiconductor field-effect transistor turn-on (threshold) voltage requirement. Finally, techniques are combined within a 1-V CMOS operational amplifier with rail-to-rail input and output ranges. While consuming 300 /spl mu/W, the 1-V rail-to-rail CMOS op amp achieves 1.3-MHz unity-gain frequency and 57/spl deg/ phase margin for a 22-pF load capacitance.

Current-sensing techniques for DC-DC converters

Current sensing is one of the most important functions on a smart power chip. Conventional current-sensing methods insert a resistor in the path of the current to be sensed. This method incurs significant power losses, especially when the current to be sensed is high. Lossless current-sensing methods address this issue by sensing the current without dissipating the power that passive resistors do. Six available lossless current sensing techniques are reviewed. A new scheme for increasing the accuracy of current sensing when the discrete elements are not known is introduced. The new scheme measures the inductor value during the DC-DC controller startup.

A low voltage, dynamic, noninverting, synchronous buck-boost converter for portable applications

With the increasing use of low voltage portable devices and growing requirements of functionalities embedded into such devices, efficient power management techniques are needed for longer battery life. Given the highly variable nature of batteries (e.g., 2.7-4.2 V for Li-ion), systems often require supply voltages to be both higher and lower than the battery voltage (e.g., power amplifier for CDMA applications), while supplying significant current, which is most efficiently generated by a noninverting buck-boost switching converter. In this paper, the design and experimental results of a new dynamic, noninverting, synchronous buck-boost converter for low voltage, portable applications is reported. The converters output voltage is dynamically adjustable (on-the-fly) from 0.4 to 4.0 V, while capable of supplying a maximum load current of 0.65 A from an input supply of 2.4-3.4 V. The worst-case response time of the converter for a 0.4 to 4 V step change in its output voltage (corresponding to a 0.2 to 2 V step at its reference input) is less than 300 /spl mu/sec and to a load-current step of 0 to 0.5 A is within 200 /spl mu/sec, yielding only a transient error of 40 mV in the output voltage. This paper also presents a nonmathematical, intuitive analysis of the time-averaged, small-signal model of a noninverting buck-boost converter.

Active capacitor multiplier in Miller-compensated circuits

A technique is presented whereby the compensating capacitor of an internally compensated linear regulator, Miller-compensated two-stage amplifier, is effectively multiplied. Increasing the capacitance with a current-mode multiplier allows the circuit to occupy less silicon area and to more effectively drive capacitive loads. Reducing physical area requirements while producing the same or perhaps better performance is especially useful in complex systems where most, if not all, functions are integrated onto a single integrated circuit. Die area in such systems is a luxury. The increasing demand for mobile battery-operated devices is a driving force toward higher integration. The enhanced Miller-compensation technique developed in this paper helps enable higher integration while being readily applicable to any process technology, be it CMOS, bipolar, or BiCMOS. Furthermore, the technique applies, in general, to amplifier circuits in feedback configuration. Experimentally, the integrated linear regulator (fabricated in a 1-/spl mu/m BiCMOS process technology) proved to be stable for a wide variety of loading conditions: load currents of up to 200 mA, equivalent series resistance of up to 3 /spl Omega/, and load capacitors ranging from 1.5 nF to 20 /spl mu/E The total quiescent current flowing through the regulator was less than 30 /spl mu/A during zero load-current conditions.

A high efficiency, soft switching DC-DC converter with adaptive current-ripple control for portable applications

A novel control scheme for improving the power efficiency of low-voltage dc-dc converters for battery-powered, portable applications is presented. In such applications, light-load efficiency is crucial for extending battery life, since mobile devices operate in stand-by mode for most of the time. The proposed technique adaptively reduces the inductor current ripple with decreasing load current while soft switching the converter to also reduce switching losses, thereby significantly improving light-load efficiency and therefore extending the operation life of battery-powered devices. A load-dependent, mode-hopping strategy is employed to maintain high efficiency over a wide load range. Hysteretic (sliding-mode) control with user programmable hysteresis is implemented to adaptively regulate the current ripple and therefore optimize conduction and switching losses. Experimental results show that for a 1-A, 5- to 1.8-V buck regulator, the proposed technique achieved 5% power efficiency improvement (from 72% to 77%) at 100 mA of load current and a 1.5% improvement (from 84% to 85.5%) at 300 mA, which constitute light-load efficiency improvements, when compared to the best reported, state-of-the-art techniques. As a result, the battery life in a typical digital signal processing microprocessor application is improved by 7%, which demonstrates the effectiveness of the proposed solution.

A 1.1-V current-mode and piecewise-linear curvature-corrected bandgap reference

A low-voltage, micropower, curvature-corrected bandgap reference is presented that is capable of working down to input voltages of 1.1 V in a relatively inexpensive process, MOSIS 2 /spl mu/m technology. This is a vanilla N-well complementary metal-oxide-semiconductor process technology with an added P-base layer. Second-order curvature correction for this reference is accomplished by a versatile piecewise-linear current-mode technique. The 0.595 V precision reference achieved a line regulation performance of 408 ppm/V for input voltages between 1.2 and 10 V. The circuit only used 14 /spl mu/A of quiescent current flow.

Optimized frequency-shaping circuit topologies for LDOs

Typical low drop-out (LDO) regulator architectures suffer from an inherent load regulation performance limitation. This limitation manifests itself through limited DC open-loop gain, and results from stringent closed-loop bandwidth requirements. The frequency response of the system is highly sensitive to the loading conditions, thereby making proper compensation a laborious endeavor. This paper discusses and addresses the limitation on regulating performance imposed by frequency compensation. Several LDO circuit topologies are subsequently developed to this end. They enhance load regulation performance by relaxing the DC open-loop gain restrictions. The circuit structures essentially alter the frequency response of the system via the error amplifier. A low drop-out regulator adopting an embodiment of the proposed technique was fabricated in the MOSIS 2-/spl mu/m process technology. The system, designed for an output capacitor of 4.7 /spl mu/F, was stable with an equivalent series resistance (ESR) ranging from 0 to 12 /spl Omega/, bypass capacitors ranging from 0 to 2.2 /spl mu/F, and a load current ranging from 0 to 50 mA.

Analysis and design of monolithic, high PSR, linear regulators for SoC applications

Linear regulators are critical analog blocks that shield a system from fluctuations in supply rails and the importance of determining their power supply rejection (PSR) performance is magnified in SoC systems, given their inherently noisy environments. In this work, a simple, intuitive, voltage divider model is introduced to analyze the PSR of linear regulators, from which design guidelines for obtaining high PSR performance are derived. The PSR of regulators that use PMOS output stages for low drop-out (LDO), crucial for modern low-voltage systems, is enhanced by error amplifiers which present a supply-correlated ripple at the gate of the PMOS pass device. On the other hand, amplifiers that suppress the supply ripple at their output are optimal for NMOS output stages since the source is now free from output ripple. A better PSR bandwidth, at the cost of dc PSR, can be obtained by interchanging the amplifiers in the two cases. It has also been proved that the dc PSR, its dominant frequency breakpoint (where performance starts to degrade), and three subsequent breakpoints are determined by the dc open-loop gain, error amplifier bandwidth, unity-gain frequency (UGF) of the system, output pole, and ESR zero, respectively. These results were verified with SPICE simulations using BSIM3 models for the TSMC 0.35 /spl mu/m CMOS process from MOSIS.