Phillip E. Allen

A low-voltage, low quiescent current, low drop-out regulator

The demand for low-voltage, low drop-out (LDO) regulators is increasing because of the growing demand for portable electronics, i.e., cellular phones, pagers, laptops, etc. LDOs are used coherently with dc-dc converters as well as standalone parts. In power supply systems, they are typically cascaded onto switching regulators to suppress noise and provide a low noise output. The need for low voltage is innate to portable low power devices and corroborated by lower breakdown voltages resulting from reductions in feature size. Low quiescent current in a battery-operated system is an intrinsic performance parameter because it partially determines battery life. This paper discusses some techniques that enable the practical realizations of low quiescent current LDOs at low voltages and in existing technologies. The proposed circuit exploits the frequency response dependence on load-current to minimize quiescent current flow. Moreover, the output current capabilities of MOS power transistors are enhanced and drop-out voltages are decreased for a given device size. Other applications, like dc-dc converters, can also reap the benefits of these enhanced MOS devices. An LDO prototype incorporating the aforementioned techniques was fabricated. The circuit was operable down to input voltages of 1 V with a zero-load quiescent current flow of 23 /spl mu/A. Moreover, the regulator provided 18 and 50 mA of output current at input voltages of 1 and 1.2 V, respectively.

Designing 1-V op amps using standard digital CMOS technology

This paper addresses the difficulty of designing 1-V capable analog circuits in standard digital complementary metal-oxide-semiconductor (CMOS) technology, Design techniques for facilitating 1-V operation are discussed and 1-V analog building block circuits are presented. Most of these circuits use the bulk-driving technique to circumvent the metal-oxide-semiconductor field-effect transistor turn-on (threshold) voltage requirement. Finally, techniques are combined within a 1-V CMOS operational amplifier with rail-to-rail input and output ranges. While consuming 300 /spl mu/W, the 1-V rail-to-rail CMOS op amp achieves 1.3-MHz unity-gain frequency and 57/spl deg/ phase margin for a 22-pF load capacitance.

Process and temperature compensation in a 7-MHz CMOS clock oscillator

This paper reports on the design and characterization of a process, temperature and supply compensation technique for a 7-MHz clock oscillator in a 0.25-/spl mu/m, two-poly five-metal (2P5M) CMOS process. Measurements made across a temperature range of -40/spl deg/C to 125/spl deg/C and 94 samples collected over four fabrication runs indicate a worst case combined variation of /spl plusmn/2.6% (with process, temperature and supply). No trimming was performed on any of these samples. The oscillation frequencies of 95% of the samples were found to fall within /spl plusmn/0.5% of the mean frequency and the standard deviation was 9.3 kHz. The variation of frequency with power supply was /spl plusmn/0.31% for a supply voltage range of 2.4-2.75 V. The clock generator is based on a three-stage differential ring oscillator. The variation of the frequency of the oscillator with temperature and process has been discussed and an adaptive biasing scheme incorporating a unique combination of a process corner sensing scheme and a temperature compensating network is developed. The biasing circuit changes the control voltage of the differential ring oscillator to maintain a constant frequency. A comparator included at the output stage ensures rail-to-rail swing. The oscillator is intended to serve as a start-up clock for micro-controller applications.

A 1.1-V current-mode and piecewise-linear curvature-corrected bandgap reference

A low-voltage, micropower, curvature-corrected bandgap reference is presented that is capable of working down to input voltages of 1.1 V in a relatively inexpensive process, MOSIS 2 /spl mu/m technology. This is a vanilla N-well complementary metal-oxide-semiconductor process technology with an added P-base layer. Second-order curvature correction for this reference is accomplished by a versatile piecewise-linear current-mode technique. The 0.595 V precision reference achieved a line regulation performance of 408 ppm/V for input voltages between 1.2 and 10 V. The circuit only used 14 /spl mu/A of quiescent current flow.

Optimized frequency-shaping circuit topologies for LDOs

Typical low drop-out (LDO) regulator architectures suffer from an inherent load regulation performance limitation. This limitation manifests itself through limited DC open-loop gain, and results from stringent closed-loop bandwidth requirements. The frequency response of the system is highly sensitive to the loading conditions, thereby making proper compensation a laborious endeavor. This paper discusses and addresses the limitation on regulating performance imposed by frequency compensation. Several LDO circuit topologies are subsequently developed to this end. They enhance load regulation performance by relaxing the DC open-loop gain restrictions. The circuit structures essentially alter the frequency response of the system via the error amplifier. A low drop-out regulator adopting an embodiment of the proposed technique was fabricated in the MOSIS 2-/spl mu/m process technology. The system, designed for an output capacitor of 4.7 /spl mu/F, was stable with an equivalent series resistance (ESR) ranging from 0 to 12 /spl Omega/, bypass capacitors ranging from 0 to 2.2 /spl mu/F, and a load current ranging from 0 to 50 mA.

A low-voltage, bulk-driven MOSFET current mirror for CMOS technology

A bulk-driven, MOSFET current mirror is described which is capable of operating at power supplies down to 1 V using standard CMOS technologies with threshold voltages in the range of /spl plusmn/0.8 V. The bulk-driven MOSFET configuration removes the requirement that the input voltage of the current mirror equal V/sub GS/>V/sub T/. At V/sub DD//V/sub SS/ of+0.75 V/-0.75 V, measurements on simple current mirrors using this new technique require only about 0.1 V across the input device of the current mirror circuit and exhibit saturation voltages on the output device of the current mirror comparable to that of standard simple current mirrors. The operation and first-order models for the bulk-driven MOSFET are presented in this paper along with the operation and experimental results of a simple, bulk-driven mirror.

A fast switching PLL frequency synthesizer with an on-chip passive discrete-time loop filter in 0.25-/spl mu/m CMOS

A phase-locked loop (PLL) frequency synthesizer with an on-chip passive discrete-time loop filter is reported in this paper. The closed loop is robust stable, and a fast switching speed is achieved by creating a stabilization zero in the discrete-time domain. The circuit implementations and system-level analysis results of the proposed architecture are presented. Techniques and design considerations are presented to overcome several potential problems of the proposed architecture, such as finite lock-in range, translation of voltage-controlled oscillator noise into in-band phase noise, and spur degradation due to clock feedthrough of the sampling switch. A 2.4 GHz prototype frequency synthesizer for Bluetooth applications was developed in a 0.25-/spl mu/m CMOS process. The measured results agree with theoretical predictions and demonstrate its high performance.

The use of current amplifiers for high performance voltage applications

A current amplifier is used to realize a voltage amplifier having an improved high frequency response and slew rate capability. It is shown that the closed loop bandwidth is independent of the closed loop voltage gain. The design and application of a unity gain and a high gain current amplifier to voltage signal processing circuits are given. The results demonstrate an efficient use of the inherent frequency response capabilities of the active devices in the circuit to achieve the amplification of high frequency and large amplitude voltage signals.

Body-driving as a low-voltage analog design technique for CMOS technology

This paper presents an overview of circuit topologies for achieving low-voltage analog designs using body-driving techniques. A new and novel low-voltage Class AB output stage is presented along with topologies for amplifiers and a four quadrant multiplier. A discussion of the application of body-driving in a silicon-on-insulator (SOI) technology is also included.

Switched-current circuits in digital CMOS technology with low charge-injection errors

In this paper, digital CMOS switched-current (SI) circuits with low charge-injection errors are presented. These circuits are based on the operation of the switches at virtual-ground nodes to result in signal-independent charge injection. Based on this scheme, different topologies for the memory cell are discussed. To verify the theoretical concepts developed, a third-order elliptic low-pass SI filter is implemented in a 0.25-/spl mu/m digital CMOS process. The filter nominally operates with a clock frequency of 10 MHz, cutoff frequency of 1 MHz, and a power supply of 2.3 V, while consuming 29 mW of power and processing input signals as large as 600-/spl mu/A peak differential. The low-charge injection nature of the circuit is reflected in its low total harmonic distortion of -59 dB for a 0.3-MHz signal with a modulation index of 0.5.