Gabriel Caffarena

SQNR estimation of fixed-point DSP algorithms

A fast and accurate quantization noise estimator aiming at fixed-point implementations of Digital Signal Processing (DSP) algorithms is presented. The estimator enables significant reduction in the computation time required to perform complex word-length optimizations. The proposed estimator is based on the use of Affine Arithmetic (AA) and it is presented in two versions: (i) a general version suitable for differentiable nonlinear algorithms, and Linear Time-Invariant (LTI) algorithms with and without feedbacks; and (ii) an LTI optimized version. The process relies on the parameterization of the statistical properties of the noise at the output of fixed-point algorithms. Once the output noise is parameterized (i.e., related to the fixed-point formats of the algorithm signals), a fast estimation can be applied throughout the word-length optimization process using as a precision metric the Signal-to-Quantization Noise Ratio (SQNR). The estimator is tested using different LTI filters and transforms, as well as a subset of non-linear operations, such as vector operations, adaptive filters, and a channel equalizer. Fixed-point optimization times are boosted by three orders of magnitude while keeping the average estimation error down to 4%.

Fast and accurate computation of the roundoff noise of linear time-invariant systems

From its introduction in the last decade, affine arithmetic (AA) has shown beneficial properties to speed up the time of computation procedures in a wide variety of areas. In the determination of the optimum set of finite word-lengths of the digital signal processing systems, the use of AA has been recently suggested by several authors, but the existing procedures provide pessimistic results. The aim is to present a novel approach to compute the round-off noise (RON) using AA which is both faster and more accurate than the existing techniques and to justify that this type of computation is restricted to linear time-invariant systems. By a novel definition of AA-based models, this is the first methodology that performs interval-based computation of the RON. The provided comparative results show that the proposed technique is faster than the existing numerical ones with an observed speed-up ranging from 1.6 to 20.48, and that the application of discrete noise models leads to results up to five times more accurate than the traditional estimations.

Optimal combined word-length allocation and architectural synthesis of digital signal processing circuits

In this brief, we address the combined application of word-length allocation and architectural synthesis of linear time-invariant digital signal processing systems. These two design tasks are traditionally performed sequentially, thus lessening the overall design complexity, but ignoring forward and backward dependencies that may lead to cost reductions. Mixed integer linear programming is used to formulate the combined problem and results are compared to the two-step traditional approach.

FPGA ACCELERATION FOR DNA SEQUENCE ALIGNMENT

In this paper, we present two new hardware architectures that implement the Smith–Waterman algorithm for DNA sequence alignment. Previous low-cost approaches based on Field Programmable Gate Array (FPGA) technology are reviewed in detail and then improved with the goal of increased performance at the same cost (i.e., area). This goal is achieved through low level optimizations aimed to adapt the systolic structure implementing the algorithm to the regular structure of FPGAs, essentially finding the optimum granularity of the systolic cells. The proposed architectures achieve processing rates close to 1 Gbps, clearly outperforming previous approaches. Comparing to the reported FPGA results of the computation of the edit-distance between two DNA sequences, throughput is doubled for the same clock frequency with a minimum area penalty. The design has been implemented on an FPGA-based prototyping board integrated into a bioinformatics system. This has allowed validating the approach in a real system (i.e., including I/O and database access), and comparing the proposed hardware solution to purely software approaches. As shown in the paper, the results are outstanding even for slow-rate buses.

Architectural synthesis of fixed-point DSP datapaths using FPGAs

We address the automatic synthesis of DSP algorithms using FPGAs. Optimized fixed-point implementations are obtained by means of considering (i) a multiple wordlength approach; (ii) a complete datapath formed of wordlength-wise resources (i.e., functional units, multiplexers, and registers); (iii) an FPGA-wise resource usage metric that enables an efficient distribution of logic fabric and embedded DSP resources. The paper shows (i) the benefits of applying a multiple wordlength approach to the implementation of fixed-point datapaths and (ii) the benefits of a wise use of embedded FPGA resources. The use of a complete fixed-point datapath leads to improvements up to 35%. And, the wise mapping of operations to FPGA resources (logic fabric and embedded blocks), thanks to the proposed resource usage metric, leads to improvements up to 54%.

Fast characterization of the noise bounds derived from coefficient and signal quantization

This paper presents a new method for computing the absolute noise bounds caused by quantization of coefficients and signals in fixed-point implementation of digital filters. A tool based on refined interval-based computations has been enhanced to calculate with reduced computational cost the implications of both effects in the finite wordlength behavior of the specific realizations. Finally, a particular filter realization is quantized using different wordlengths and the computed bounds are presented for comparison.

Design and Implementation of a Hardware Module for Equalisation in A 4G MIMO Receiver

In this paper we address the implementation on FPGAs of a 4G equaliser for a multiple-input multiple-output (MIMO) receiver. It is embedded in a multi-carrier code-division multiple-access (MC-CDMA) radio system, which is able to handle up to 32 users and provide transmission bit-rates up to 125 Mbps. We provide details on decisions taken for the design of the signal processing algorithm, including floating-point to fixed-point translation and architectural considerations. Implementation results using Xilinx Virtex-4 devices are finally reported

High-Level Synthesis of Multiple Word-Length DSP Algorithms Using Heterogeneous-Resource FPGAs

In this paper we address the high-level synthesis of multiple word-length DSP algorithms over programmable devices (FPGAs). Previous approaches tend to simplify the set of resources, thus alleviating the complexity of the high-level synthesis, but leading to non-optimal solutions. Here, we present a high-level synthesis framework that overcomes these limitations by means of considering: (i) both logic-based and embedded multipliers, (ii) both constant and generic multipliers and (iii) variable latency resources. A simulated annealing based approach for the combined scheduling, resource allocation and binding tasks is presented. When compared to previous approaches, area improvements of up to 60% are reported

FPGA for pseudorandom generator cryptanalysis

Abstract FPGAs have been successfully applied for cryptanalytic purposes, particularly in exhaustive key search that is a highly parallelizable task. In this work, we consider a pseudorandom generator scheme that consists of a number of subgenerators, the first of which is a linear feedback shift register (LFSR). LFSR is often used in cipher systems because of good cryptographic characteristics of its output sequence. The cryptanalysis has shown that if noisy prefix of the output sequence of this generator is known, it is possible to reconstruct the initial state of the LFSR by means of generalized correlated attack. The attack is based on the resolving of the constrained edit distance between the sequences determined by the initial states of the shift registers and the intercepted noisy output sequence. The systolic array architecture exploits the intrinsic parallelism of the dynamic programming algorithm for edit distance computation and achieve reductions in computation time of several orders of magnitude comparing with sequential calculation that is characteristic for software solutions. With a minimum increase of area, our design doubles the speed of similar approaches that are applied in bioinformatics, since there are no published ones for cryptanalysis. The obtained results on Xilinx Virtex and Virtex2 FPGA families also holds when a bus is connected, since our design takes into account the bus I/O bottleneck (i.e. PCI).

A Formal Method for Optimal High-Level Casting of Heterogeneous Fixed-Point Adders and Subtractors

Fixed-point arithmetic datapaths with heterogeneous scaling and wordlengths are commonplace in resource, latency, or power constrained designs. This paper describes and proves correct a formal method for accurate high-level casting of optimal adders and subtractors. The proposed approach allows for an early accurate estimation of resource usage which is then available for high-level decision-taking in the design flow. As a result, decoupling between high-level and low-level synthesis is achieved. Results concerning the impact of the approach on resource estimates and a discussion on the wide applicability of the method are presented.