Gael Blondel

High current repetitive avalanche of low voltage trench power MOSFETs

The capability of 20V trench power MOSFETs to withstand high current repetitive avalanche events has been investigated. Automotive standard 20V BVdss rated MOSFETs with active area of 21mm2 have been successfully subjected with up to 300 million 59µs duration avalanche events at peak currents up to 135A whilst held at an average junction temperature of 150°C. The effect of cell pitch on parameter shifts has been investigated by applying avalanche currents up to 200A (9.5A/mm2). It has been found that reduced cell pitch increases the stability of threshold voltage and on-state resistance whilst suffering from increased drain-source leakage.

Preliminary failure-mode characterization of emerging direct-lead-bonding power module. Comparison with standard wire-bonding interconnection

Abstract Direct-lead-bonding (DLB) and wire-bonding, in epoxy-moulded package, are compared in terms of functional characteristics, failure-mode and post-fault high-current capability of a dual-chip power module (PM), with respect to I 2 T and critical energy. Wire-bonding power modules have shown poor thermal behaviour, a high and unstable R CE (the chip fault residual resistance), and sometimes a fuse-effect when used in gel-filled power modules. However, DLB power modules demonstrated a very good thermal and electrical behaviour, a very low and stable R CE under high energy failure. After non-destructive defect localization thanks to Lock-In Thermography coupled to RX tomography, the authors were able to confirm the formation of a metallic bridge under wire-bondings and through the chips and solder in DLB, which explains low R CE values for this technology. The DLB interconnection appears to be a promising technology for power module. Nevertheless, the absence of wire-fuse-effect in case of extreme failure, compared to classical wire-bonding, leads the authors to rethink fail-safe and fault-tolerant strategies for critical converter.

A compact transient electrothermal model for integrated power systems: Automotive application

The paper is about a so-called ”diffusive representation”, a new modeling dynamic systems method and its application to efficient transient thermal modeling of multichip power module taking into account thermal coupling effects. Compact thermal models are required for many analyses during the design of power systems. Generally a RC-ladder model is used and analytical expressions enable to quantify R and C values. Unfortunately the trade-off between complexity, convergence and accuracy is hard to settle. Diffusive approximation of the heat law equation offers an alternative representation. The compact thermal model is a state space model. Parameters identification procedures are given and are validated. The method is applied on an inverter leg, a 400A MOSFET power module manufactured by VALEO for starter-alternator system. Electrothermal measurements have been achieved to develop an electrical model with thermo-sensitive parameters of the MOSFET dies. Electro-thermal measurements and 3D Finite Element thermal simulations have been performed for validations. A compact diffusive model comes as a state space model and may be easily implemented in a ”circuit” simulator.

Failure to short-circuit capability of emerging direct-lead-bonding power module. Comparison with standard interconnection. Application for dedicated fail-safe and fault-tolerant converters embedded in critical applications

The Direct-Lead-Bonding (DLB) interconnection appears to be a promising technology for power-module (PM). Nevertheless, the absence of wire-fuse-effect in case of extreme failure, compared to classical wire-bonding, leads authors to rethink fail-safe and fault-tolerant strategies for critical converter. Therefore, this paper will provide a comparative study between these two designs in terms of failure-mode and post-fault high-current capability.

Self-heating analysis of power MOSFET module during burn-in test

The paper deals with the thermal behavior for paralleled MOSFETs module during accelerated cycling burn-in test in harsh ambient and current conditions. The aim of the work is to optimize the key parameters acting on the self-heating in order to avoid undesirable failures resulting from overheating. An electro-thermal model is developed to simulate the device temperature during the test. Well calibrated to the experimental data for Ron and avalanche phases, our model allowed realistic thermal prediction. The impact of gate bias, pulse time, as well as disparities of breakdown voltage between the FETs was analyzed and the test conditions were optimized.

Experimental setup for measuring the local temperature of active electronic components

A novel non-destructive and non-contacting technique for the local temperature measurement of heat spot in electronic component is presented. Highly-sensitive lock-in near infrared (NIR) thermography is used to localize the heat spot induced temperature variations down to 10-1°C at a lateral resolution down to 3 μm. Speedy temperature evolution about 10 microseconds can be followed as using an integral InGaAs PIN photodiode assembled with the matched preamplifier.