Ganapati Srinivasa

QuickIA: Exploring heterogeneous architectures on real prototypes

Over the last decade, homogeneous multi-core processors emerged and became the de-facto approach for offering high parallelism, high performance and scalability for a wide range of platforms. We are now at an interesting juncture where several critical factors (smaller form factor devices, power challenges, need for specialization, etc) are guiding architects to consider heterogeneous chips and platforms for the next decade and beyond. Exploring heterogeneous architectures is challenging since it involves re-evaluating architecture options, OS implications and application development. In this paper, we describe these research challenges and then introduce a heterogeneous prototype platform called QuickIA that enables rapid exploration of heterogeneous architectures employing multiple generations of Intel processors for evaluating the implications of asymmetry and FPGAs to experiment with specialized processors or accelerators. We also show example case studies using the QuickIA research prototype to highlight its value in conducting heterogeneous architecture, OS and applications research.

Scaling the "memory wall"

DRAM has been the technology for computer main memory since Intel released the first commercial DRAM chip (i1103) in 1970. As technology scales and demand for memory performance, it seems DRAM is facing several challenges. Many other memory technologies are anticipated to replace it but none has emerged as a clear winner thus far. In this paper we post the question. Is it possible to re-examine the design of DRAM to continue its life for another decade at least?

Trace alignment algorithms for offline workload analysis of heterogeneous architectures

Heterogeneous architectures with single-ISA asymmetric cores have the potential to improve both the performance and energy efficiency of software execution by dynamically selecting the most appropriate core type to run each execution thread. In this paper, we propose a trace-based methodology to explore power and performance benefits of single-ISA heterogeneous core architectures. The basic idea is to collect multiple traces by running a workload on different homogeneous platforms, and to align these traces for offline analysis. For this, we propose a wavelet-based similarity metric, which captures both fine-grain and coarse-grain software phases across different traces. Then, we propose a scalable dynamic programming algorithm to optimize this metric to align the traces. Our experiments show that the runtime and energy values predicted by our offline methodology have good accuracy with respect to the real measurements from a prototype heterogeneous system. The proposed methodology can enable design space exploration of single-ISA heterogeneous multi-core systems using traces from off-the-shelf homogeneous systems.

Evolution of the server processor/platform architecture and the critical role of interconnect and future challenges

Peering at the next decade, will explore the processor and platform architecture challenges, as to what areas are undergoing enormous changes, while surveying the learning over the past two decades. While exploring the next decade, will look at the processor internal interconnect evolution along with on chip resources starting with cache, memory controller and now being followed by IO integration vis-à-vis interchip multisocket interconnect at the platform level. Doing this, will outline the lessons learnt, what are the key challenges at macro and micro architecture level from the current perspective, where it is trending and some projections. I will describe the daily challenges and how we find sweet spots and surmount these in the interconnect area. The talk will emphasize the three key vectors architects wrestle with Power, Performance and Cost at the processor and platform level and the critical role played by interconnect. The interconnect matters in architecting server that include power, flexibility, bandwidth and latency at macro and micro level. Interconnect could make or break in the product continuity and is a matter of serious consequence. We will explore how these affect the picture at a bigger level be it rack or cluster or data center. With the current trend on Chip Multiprocessing mostly homogeneous that we have, will discuss the growth challenges that industry will face, what are the murky areas and state of SW and computing Industries key challenges. Will explore Heterogeneous computing, power and parallelization aspects and where we need a lot of research and focus.

Wavelet-Based Trace Alignment Algorithms for Heterogeneous Architectures

Heterogeneous architectures with single-instruction set architecture (ISA) asymmetric cores can improve both the performance and energy efficiency of software execution by dynamically selecting the most appropriate core type to run each execution thread. In this paper, we propose a trace-based methodology to explore power and performance benefits of single-ISA heterogeneous core architectures. The basic idea is to collect multiple traces by running a workload on different homogeneous platforms, and to align these traces for offline analysis. For this, we propose a wavelet-based similarity metric, which captures both fine-grain and coarse-grain software phases across different traces. Then, we propose a scalable dynamic programming algorithm to optimize this metric to align the traces. Our experiments show that the runtime and energy values predicted by our offline methodology have good accuracy with respect to the real measurements from a prototype heterogeneous system.

Heterogeneity and interconnect

The current usage of client devices - smart phones, tracking devices and wearable electronics - force us to take a deep look at energy consumption, they demand long battery life. Energy needs also get exacerbated by the demands of high level of connectivity, the Always On Always Connected usage model expected of such devices. We are unable to predict the demands on these devices or the usable models two to three years down the future. But few things are certain, namely the demand for higher power, energy efficiency and a wide dynamic range of operation. The talk will explore the trends and show how these affect the hardware and software architecture and its directions. In particular, the heterogeneity of mixing various types of processing elements, accelerators with a flexible interconnect fabric will be explored and some architectural findings on flexible interconnect and 3DIC will be shared.