Eliezer Weissmann

Power-Management Architecture of the Intel Microarchitecture Code-Named Sandy Bridge

Modern microprocessors are evolving into system-on-a-chip designs with high integration levels, catering to ever-shrinking form factors. Portability without compromising performance is a driving market need. An architectural approach thats adaptive to and cognizant of workload behavior and platform physical constraints is indispensable to meeting these performance and efficiency goals. This article describes power-management innovations introduced on Intels Sandy Bridge microprocessor.

H-EARtH: Heterogeneous Multicore Platform Energy Management

By scheduling each workload according to its most advantageous core and managing voltage and frequency, the heterogeneous energy-aware race to halt (H-EARtH) algorithm optimizes CPU platform energy.