Ganesan Umanesan

A class of random multiple bits in a byte error correcting and single byte error detecting (S/sub t/b/EC-S/sub b/ED) codes

Correcting multiple random bit errors that corrupt a single DRAM chip becomes very important in certain applications, such as semiconductor memories used in computer and communication systems, mobile systems, aircraft, and satellites. This is because, in these applications, the presence of strong electromagnetic waves in the environment or the bombardment of an energetic particle on a DRAM chip is highly likely to upset more than just one bit stored in that chip. On the other hand, entire chip failures are often presumed to be less likely events and, in most applications, detection of errors caused by single chip failures are preferred to correction due to check bit length considerations. Under this situation, codes capable of correcting random multiple bit errors that are confined to a single chip output and simultaneously detecting errors caused by single chip failures are attractive for application in high speed memory systems. This paper proposes a class of codes called Single t/b-error Correcting-Single b-bit byte Error Detecting (S/sub t/b/EC-S/sub b/ED) codes which have the capability of correcting random t-bit errors occurring within a single b-bit byte and simultaneously indicating single b-bit byte errors. For the practical case where the chip data output is 8 bits, i.e., b = 8, the S/sub 3/8/EC-S/sub 8/ED code proposed in this paper, for example, requires only 12 check bits at information length 64 bits. Furthermore, this S/sub 3/8/EC-S/sub 8/ED code is capable of correcting errors caused by single subarray data faults, i.e., single 4-bit byte errors, as well. This paper also shows that perfect S/sub (b-t)/b/EC-S/sub b/ED codes, i.e., perfect S/sub t/b/EC-S/sub b/ED codes for the case where t = b - 1, do exist and provides a theorem to construct these codes.

Parallel decoding cyclic burst error correcting codes

Burst error correcting codes have traditionally been decoded using linear feedback shift registers (LFSR). However, these sequential decoding schemes are not suitable for applications where a high speed parallel decoding employing only combinational logic circuitry is required. This paper presents a simplified method for parallel decoding burst error correcting cyclic codes, which does not involve any matrix inversions.

A class of random multiple bits in a byte error correcting (S/sub t/b/EC) codes for semiconductor memory systems

Recent high density wide I/O DRAM chips are highly vulnerable to multiple random bit errors. Therefore, correcting multiple random bit errors that corrupt a single DRAM chip becomes very important in certain applications, such as semiconductor memories used in computer and communication systems, mobile systems, aircraft and satellites. This is because, in these applications, the presence of strong electromagnetic waves in the environment or the bombardment of an energetic particle on a DRAM chip is likely to upset more than just one bit stored in that chip. Under this situation, codes capable of correcting random multiple bit errors that are confined to a single DRAM chip output are suitable for application in high speed semiconductor memory systems. This paper proposes a class of codes called single t/b-error correcting (S/sub t/b/EC) codes which are capable of correcting random t-bit errors occurring within a single b-bit byte. For the case where the chip data output is 16 bits, i.e., b = 16, the S/sub 3/16/EC code proposed in this paper requires only 16 check bits, that is, only one chip is required for check bits at practical information lengths such as 64, 128 and 256 bits. Furthermore, this S/sub 3/16/EC code is capable of detecting more than 95% of all single 16 bit byte errors at information length 64 bits.

Single byte error control codes with double bit within a block error correcting capability for semiconductor memory systems

Computer memory systems when exposed to strong electromagnetic waves or radiation are highly vulnerable to multiple random bit errors. Under this situation, we cannot apply existing SEC-DED or S/sub b/EC capable codes because they provide insufficient error control performance. This correspondence considers the situation where two random bits in a memory chip are corrupted by strong electromagnetic waves or radioactive particles and proposes two classes of codes that are capable of correcting random double bit errors occurring within a chip. The proposed codes, called Double bit within a block Error Correcting-Single byte Error Detecting ((DEC)/sub B/-S/sub b/ED) code and Double bit within a block Error Correcting-Single byte Error Correcting ((DEC)/sub B/-S/sub b/EC) code, are suitable for recent computer memory systems.

A class of random multiple bits within a byte error correcting codes with single byte error detecting capability for memory systems

We propose a class of codes called single t-bits within a b-bit byte error correcting-single b-bit byte error detecting (S/sub t/b/EC-S/sub b/ED) code for high speed semiconductor memory systems.

Single byte error control codes with adjacent double bit error correcting capability for computer memory systems

We propose a class of codes called adjacent double bit error correcting-single byte error detecting (ADEC-S/sub b/ED) codes for high speed semiconductor memory systems.