Eiji Fujiwara

Error-control coding in computers

In this article, intended for readers with basic knowledge in coding, the codes used in actual systems are surveyed. Error control in high-speed memories is examined, including bit-error-correcting/detecting codes, byte-error-correcting/detecting codes, and codes to detect single-byte errors as well as correct single-bit errors and detect double-bit errors. Tape and disk memory codes for error control in mass memories are discussed. Processor error control and unidirectional error-control codes are covered, including the application of the latter to masking asymmetric line faults.<<ETX>>

A Self-Checking Generalized Prediction Checker and Its Use for Built-In Testing

This paper presents a new design for a ¿self-checking checker for nonencoded multiinput combinational circuits. A built-in testing method is also stressed. The proposed checker, called a generalized prediction checker (GPC), has an extended and generalized form of conventional parity prediction checkers, and includes a duplication checker as a special case. A parity check matrix H imparts arbitrary error detection ability to the new GPC. The GPC is made perfectly self-testing by applying a new method that adds one extra input to the cascaded multiinput comparator and to the cascaded XOR tree circuit in the GPC. This extra input may take any value during normal operation. The ¿self-checking GPC is implemented for specific circuit examples and verified. For these examples, the ¿self-checking GPCs show 100 percent fault coverage for single stuck faults in both the circuit under check and the checker itself. Using this checker, the built-in testing method taking advantage of the checkers automatic fault detection ability is shown to be suitable for testing combinational circuits.

A class of random multiple bits in a byte error correcting and single byte error detecting (S/sub t/b/EC-S/sub b/ED) codes

Correcting multiple random bit errors that corrupt a single DRAM chip becomes very important in certain applications, such as semiconductor memories used in computer and communication systems, mobile systems, aircraft, and satellites. This is because, in these applications, the presence of strong electromagnetic waves in the environment or the bombardment of an energetic particle on a DRAM chip is highly likely to upset more than just one bit stored in that chip. On the other hand, entire chip failures are often presumed to be less likely events and, in most applications, detection of errors caused by single chip failures are preferred to correction due to check bit length considerations. Under this situation, codes capable of correcting random multiple bit errors that are confined to a single chip output and simultaneously detecting errors caused by single chip failures are attractive for application in high speed memory systems. This paper proposes a class of codes called Single t/b-error Correcting-Single b-bit byte Error Detecting (S/sub t/b/EC-S/sub b/ED) codes which have the capability of correcting random t-bit errors occurring within a single b-bit byte and simultaneously indicating single b-bit byte errors. For the practical case where the chip data output is 8 bits, i.e., b = 8, the S/sub 3/8/EC-S/sub 8/ED code proposed in this paper, for example, requires only 12 check bits at information length 64 bits. Furthermore, this S/sub 3/8/EC-S/sub 8/ED code is capable of correcting errors caused by single subarray data faults, i.e., single 4-bit byte errors, as well. This paper also shows that perfect S/sub (b-t)/b/EC-S/sub b/ED codes, i.e., perfect S/sub t/b/EC-S/sub b/ED codes for the case where t = b - 1, do exist and provides a theorem to construct these codes.

Probability to achieve TSC goal

We propose a probabilistic measure for self-checking (SC) circuits that is analogous to reliability of fault-tolerant systems. This measure is defined as the probability to achieve totally self-checking (TSC) goal at the lth cycle: TSCG(t). TSCG provides insight to the worst case dynamic behavior of SC circuits with respect to the application environment and component failure rates. TSCG surpasses the TSC definitions in determining the applicability of a circuit in a given application environment. An SC circuit achieves TSC goal when no erroneous information or data is propagated beyond the boundary of this circuit. TSCG is therefore the probability that this fault confinement mechanism is intact. The SC properties are obtained through adding hardware redundancy to the original digital design, which means that an SC circuit has a higher failure rate than the original circuit. Further, there are tradeoffs between the level of hardware redundancy, the reliability, and the TSCG. We give several examples to clearly demonstrate these tradeoffs for different design environments. We emphasize that the TSCG is intended to provide a mean of dynamic error handling performance evaluation of SC designs. The TSC definitions and alike are still intact, since a cost-effective SC circuit must begin with a TSC circuit. The TSCG gives confidence in the use of cost-efficient error control codes and/or reduction in error handling capability. Analogous to reliability, the TSCG can be used in product specifications. This is a crucial step toward the practical applications of TSC or CED circuits.

A General Class of M-Spotty Byte Error Control Codes

Error control codes have extensively been applied to semiconductor memories using high density RAM chips with wide I/O data, e.g., with 8-bit or 16-bit I/O data. Recently, spotty byte errors called s-spotty byte errors are newly defined as t or fewer bits errors in a byte having length b bits, where 1 ≤ t ≤ b. This paper proposes another type of spotty byte errors, i.e., m-spotty byte errors, where more than t bits errors in a byte may occur due to hit by high energetic particles. For these errors, this paper presents generalized m-spotty byte error control codes with minimum m-spotty distance d.

A class of error control codes for byte organized memory systems-SbEC-(Sb+S)ED codes

A new class of error control codes, single byte error correcting and single byte plus single bit error detecting codes, are presented. The codes are suitable for semiconductor memory systems organized in a b-bit-per-chip manner, b/spl ges/2, and more efficient than previously known codes with as strong error control capabilities.

A class of M-ary asymmetric symbol error correcting codes for data entry devices

Nonbinary M-ary symbols such as alphanumeric characters are commonly used in data entry devices, e.g., keyboards and character recognition devices. The M-ary symbols processed by these devices are sometimes mistaken for other symbols due to errors such as mistyping in keyboards or misreading in character recognition systems. These errors are generally asymmetric, not symmetric. For example, the symbols corresponding to adjacent keys in a keyboard have a high error probability due to mistapping. Similarly, in character recognition systems, two symbols having similar shape have high error probability to be misrecognized. These asymmetric errors can be corrected or detected by using M-ary asymmetric symbol error control codes. We propose a new class of M-ary single asymmetric symbol error correcting codes by using a new class of rings obtained from a direct product of Galois fields. Asymmetric symbol errors are expressed by an error directionality graph, based on which the error correction capability of the codes is determined. The code is defined by a parity check matrix over the ring and functions which map a set of M-ary symbols into the ring. One of the functions is derived from the graph coloring problem of the error directionality graph. The proposed codes have greater information symbol length than the existing M-ary single symmetric symbol error correcting codes.

A class of error-locating codes for byte-organized memory systems

Error-locating codes (EL codes), first proposed by J.K. Wolf and B. Elspas in 1963, have the potential to be used to identify the faulty module for fault isolation and reconfiguration in fault-tolerant computer systems. This paper proposes a new class of EL codes suitable for memory systems organized with b-bit (b/spl ges/2) byte-organized semiconductor memory chips that are mounted on memory cards each having B-bit width. The proposed linear code, called the S/sub b/B/EL code, identifies erroneous memory card locations containing a faulty byte-organized chip. Another linear code proposed in this paper, the SEC-S/sub b/B/EL code, corrects single-bit errors induced by alpha particles and, for byte errors, it locates erroneous card positions containing a faulty chip. This paper describes design methods of the proposed codes and shows an evaluation of the decoding hardware and the error detection capabilities. >

Single b-bit byte error correcting and double bit error detecting codes for high-speed memory systems

The authors propose a novel design method for single b-bit byte error correcting and double bit error detecting code, called Sb EC-DED code, suitable for high-speed memory systems using byte organized RAM chips. This type of byte error control code is practical from the viewpoint of having less redundancy and stronger error control capability than the existing codes. A code design method using elements from a coset of a subfield under addition gives the practical Sb EC-DED code with 64 information bits and 4-bit byte length which has the same check-bit length, 12 bits, as that of the single byte error correcting code. This also has very high error detection capabilities of random double byte errors and of random triple bit errors.<<ETX>>

Masking asymmetric line faults using semi-distance codes

The authors propose a masking method for asymmetric line faults in LSIs using semidistance codes, which are a class of nonlinear codes. Faults caused by open or short circuit defects in line areas of LSIs can be made asymmetric by controlling the bus driver and the bus terminal gates. The conditions required for codes to mask these faults are clarified, and the codes satisfying these conditions for random faults and adjacent faults caused by line bridging defects are constructed by using a novel concept of semidistance. This masking technique has the advantage that no additional circuits, such as error decoders, are needed. The codes have been applied to the bus lines in the address decoders of the 4-Mb ROMs to improve fabrication yield of the LSIs.<<ETX>>