Ganesh Kothapalli

Comparison between Neural Network based PI and PID controllers

The Pneumatic actuation systems are widely used in industrial automation, such as drilling, sawing, squeezing, gripping, and spraying. Also, they are used in motion control of materials and parts handling, packing machines, machine tools, and in robotics; e.g. two-legged robot. In this paper, a Neural Network based PI controller and Neural Network based PID controller are designed and simulated to increase the position accuracy in a pneumatic servo actuator. In these designs, a well-trained Neural Network provides these controllers with suitable gains depending on feedback representing changes in position error and changes in external load force. These gains should keep the positional response within minimum overshoot, minimum rise time and minimum steady state error. A comparison between Neural Network based PI controller and Neural Network based PID controller was made to find the best controller that can be generated with simple structure according to the number of hidden layers and the number of neurons per layer. It was concluded that the Neural Network based PID controller was trained and generated with simpler structure and minimum Mean Square Error compared with the trained and generated one used with PI controller.

Influence of neural network training parameters on short-term wind forecasting

This paper investigates factors which can affect the accuracy of short-term wind speed prediction when done over long periods spanning different seasons. Two types of neural networks (NNs) are used to forecast power generated via specific horizontal axis wind turbines. Meteorological data used are for a specific Western Australian location. Results reveal that seasonal variations affect the prediction accuracy of the wind resource, but the magnitude of this influence strongly depends on the details of the NN deployed. Factors investigated include the span of the time series needed to initially train the networks, the temporal resolution of these data, the length of training pattern within the overall span which is used to implement the predictions and whether the inclusion of solar irradiance data can appreciably affect wind speed prediction accuracy. There appears to be a relatively complex relationship between these factors and the accuracy of wind speed prediction via NNs. Predicting wind speed based on NNs trained using wind speed and solar irradiance data also increases the prediction accuracy of wind power generated, as can the type of network selected.

An analogue recurrent neural network for trajectory learning and other industrial applications

A real-time analogue recurrent neural network (RNN) can extract and learn the unknown dynamics (and features) of a typical control system such as a robot manipulator. The task at hand is a tracking problem in the presence of disturbances. With reference to the tasks assigned to an industrial robot, one important issue is to determine the motion of the joints and the effector of the robot. In order to model robot dynamics we use a neural network that can be implemented in hardware. The synaptic weights are modelled as variable gain cells that can be implemented with a few MOS transistors. The network output signals portray the periodicity and other characteristics of the input signal in unsupervised mode. For the specific purpose of demonstrating the trajectory learning capabilities, a periodic signal with varying characteristics is used. The developed architecture, however, allows for more general learning tasks typical in applications of identification and control. The periodicity of the input signal ensures convergence of the output to a limit cycle. Online versions of the synaptic update can be formulated using simple CMOS circuits. Because the architecture depends on the network generating a stable limit cycle, and consequently a periodic solution which is robust over an interval of parameter uncertainties, we currently place the restriction of a periodic format for the input signals. The simulated network contains interconnected recurrent neurons with continuous-time dynamics. The system emulates random-direction descent of the error as a multidimensional extension to the stochastic approximation. To achieve unsupervised learning in recurrent dynamical systems we propose a synapse circuit which has a very simple structure and is suitable for implementation in VLSI.

Assessment of Artificial Neural Networks and IHACRES models for simulating streamflow in Marillana catchment in the Pilbara, Western Australia

Abstract A wide range of techniques are available to model hydrological processes. Choosing a model is not a straightforward task considering geographical and climate conditions. Although this is an exercise with some level of uncertainty it does help to understand hydrological processes which are used for the management and development of water resources. In Western Australia with its arid or semi-arid climate, water resource management is a key issue for future sustainable development. In this study, IHACRES, a physical-based hydrology model, and Artificial Neural Networks were used to simulate the daily water discharge from Marillana Creek catchment in the Pilbara in Western Australia. Although, these models did not produce satisfactory results, the comparison of the results show that the ANN model can be a feasible alternative for complex hydrology systems with poor recorded data. Also, data from two neighbouring gauges were successfully used to improve the result of Artificial Neural Networks over the IHACRES model.

Compensation of a winner take all circuit

The design and simulation results of a CMOS winner-take-all (WTA) circuit are presented. A 16-cell test circuit has been designed for intended implementation in an 0.18 /spl mu/m CMOS process. This paper describes the architecture and design issues related to a CMOS WTA circuit. Several design issues such as high resolution, high speed, low power consumption, compactness, and high input voltage range have been addressed. The proposed circuit has a compact configuration of complexity O(N) where N denotes input count. It seems to be very suitable, especially for charge-based applications where input vectors are generated by a set of charged capacitances.

A parameter search technique to build an ARMA model

The parameter search technique allows us to approximate a high-order model by a much lower order autoregressive moving average (ARMA) model with a performance that is nearly indistinguishable from the original. Parameter estimation for a system or its model can be achieved through iterative techniques. The problem is considered as one of minimising an error function. The error is defined as the difference between the expected value and the actual value obtained from an initial approximate model. Through iteration the model parameters are refined. Such a recursive parameter estimator (RPE) can be used to greatly reduce the order of certain digital filters with little distortion to their frequency and phase responses. Since digital filters are commonly used in electronic communications and signal processing applications, RPE may be a tool of considerable practical use. To demonstrate this potential, RPE is applied to an FIR model, showing that its order may be reduced considerably with little change to the accuracy of the model.

A CMOS realizable recurrent neural network for signal identification

The architecture of an analog recurrent neural network that can learn a continuous-time trajectory is presented. The proposed learning circuit does not distinguish parameters based on a presumed model of the signal or system for identification. The synaptic weights are modeled as variable gain cells that can be implemented with a few MOS transistors. The network output consists primarily of neuron signals which portray the periodic characteristics of the input signal in unsupervised mode. For the specific purpose of demonstrating the trajectory learning capabilities, a periodic signal with varying characteristics is used. The developed architecture, however, allows for more general learning tasks typical in applications of identification and control. The periodicity of the input signal ensures consistency in the outcome of the error and convergence speed at different instances in time. While alternative on-line versions of the synaptic update measures can be formulated, which allow for faster learning speed and better convergence behavior, the architecture of the analog RNN used here is easier to implement while still allowing to demonstrate the general principle. Because the architecture depends on the network generating a stable limit cycle, and consequently a periodic solution which is robust over an interval of parameter uncertainties, we currently place the restriction of a periodic format for the input signals. The simulated network contains interconnected recurrent neurons with continuous-time dynamics. The system basically performs random-direction descent of the error as a multidimensional extension to the stochastic approximation. To achieve unsupervised learning in recurrent dynamical systems we propose a synapse circuit which has a very simple structure and is suitable for implementation in VLSI.

Excitation modes and transient response of a winner-take-all circuit

Design and simulation results of CMOS winner-take-all circuit are presented. A 16-cell test circuit has been designed for intended implementation in 0.18 /spl mu/m CMOS process. This paper describes the architecture and design issues related to a CMOS WTA circuit. The proposed circuit has a compact configuration of complexity O(N) where N denotes input count. It seems to be very suitable, especially for charge-based applications where input vectors are generated by a set of charged capacitances. The WTA is a very versatile network. The circuit has the potential to exhibit multiple winners under certain circumstances. This study investigates the dynamics of a WTA networks behaviour which lead to multiple winner selection.

A hysteretic comparator’s influence on a current-mode ADC

A low-voltage low-power CMOS switched-current analog-to-digital converter is presented. The influences of a hysteretic comparator on the performance of the ADC are studied with the help of SPICE simulations. SPICE BSIM4 models are used to study the behavior of the overall circuit. The hysteretic comparator is devised to minimize the errors caused by current spikes at the input to the comparator. The current-mode A/D converter implements a multiply-by-2 scheme. The A/D converter starts converting for the most significant bit (MSB) of an input current. The input is multiplied by two using MOS transistors. The comparator then senses the current imbalance and then determines if the signal 2Iin is greater than Iref. The remaining bits are converted in the same manner. The aim of this study is to use such an ADC in the CMOS imagers to be realized in a low-cost standard digital process technology. Another aim of this study is to utilize a hysteretic comparator to quantize the full-scale range of signals (MSB to LSB) independent of the resolution. The proposed design allows users to easily set the hysteresis width of the comparator for a predetermined resolution without causing any performance degradation.

ADC performance limitations due to quantizer non-idealities

A low-voltage low-power CMOS Sigma-Delta Modulator (SDM) is presented. The influence of a dynamic latched comparator on the performance of the SDM are studied with the help of SPICE simulations. SPICE BSIM4 models are used to study the transient behaviour of the overall circuit. The latched comparator is devised to be used to detect very small differential signals in the presence of large common-mode signals. An 8-bit second-order Sigma-Delta Modulator is used to demonstrate the limitations and potential, solutions associated with the use of the latched comparator. The aim of this study is to use such an ADC in the CMOS imagers to be realized in a low-cost standard digital process technology. Another aim of this study is to utilize an identical design layout of the latched comparator to quantize the full-scale range of signals (LSB to MSB).