Kamran Eshraghian

Memristor MOS Content Addressable Memory (MCAM): Hybrid Architecture for Future High Performance Search Engines

Large-capacity content addressable memory (CAM) is a key element in a wide variety of applications. The inevitable complexities of scaling MOS transistors introduce a major challenge in the realization of such systems. Convergence of disparate technologies, which are compatible with CMOS processing, may allow extension of Moores Law for a few more years. This paper provides a new approach towards the design and modeling of Memory resistor (Memristor)-based CAM (MCAM) using a combination of memristor MOS devices to form the core of a memory/compare logic cell that forms the building block of the CAM architecture. The non-volatile characteristic and the nanoscale geometry together with compatibility of the memristor with CMOS processing technology increases the packing density, provides for new approaches towards power management through disabling CAM blocks without loss of stored data, reduces power dissipation, and has scope for speed improvement as the technology matures.

The fourth element: characteristics, modelling and electromagnetic theory of the memristor

In 2008, researchers at the Hewlett–Packard (HP) laboratories published a paper in Nature reporting the development of a new basic circuit element that completes the missing link between charge and flux linkage, which was postulated by Chua in 1971 (Chua 1971 IEEE Trans. Circuit Theory 18, 507–519 (doi:10.1109/TCT.1971.1083337)). The HP memristor is based on a nanometre scale TiO2 thin film, containing a— doped region and an undoped region. Further to proposed applications of memristors in artificial biological systems and non-volatile RAM, they also enable reconfigurable nanoelectronics. Moreover, memristors provide new paradigms in application-specific integrated circuits and field programmable gate arrays. A significant reduction in area with an unprecedented memory capacity and device density are the potential advantages of memristors for integrated circuits. This work reviews the memristor and provides mathematical and SPICE models for memristors. Insight into the memristor device is given via recalling the quasi-static expansion of Maxwell’s equations. We also review Chua’s arguments based on electromagnetic theory.

Memristive Device Fundamentals and Modeling: Applications to Circuits and Systems Simulation

The nonvolatile memory property of a memristor enables the realization of new methods for a variety of computational engines ranging from innovative memristive-based neuromorphic circuitry through to advanced memory applications. The nanometer-scale feature of the device creates a new opportunity for realization of innovative circuits that in some cases are not possible or have inefficient realization in the present and established design domain. The nature of the boundary, the complexity of the ionic transport and tunneling mechanism, and the nanoscale feature of the memristor introduces challenges in modeling, characterization, and simulation of future circuits and systems. Here, a deeper insight is gained in understanding the device operation, leading to the development of practical models that can be implemented in current computer-aided design (CAD) tools.

An Analytical Approach for Memristive Nanoarchitectures

As conventional memory technologies are challenged by their technological physical limits, emerging technologies driven by novel materials are becoming an attractive option for future memory architectures. Among these technologies, Resistive Memories (ReRAM) created new possibilities because of their nanofeatures and unique I-V characteristics. One particular problem that limits the maximum array size is interference from neighboring cells due to sneak-path currents. A possible device level solution to address this issue is to implement a memory array using complementary resistive switches (CRS). Although the storage mechanism for a CRS is fundamentally different from what has been reported for memristors (low and high resistances), a CRS is simply formed by two series bipolar memristors with opposing polarities. In this paper, our intention is to introduce modeling principles that have been previously verified through measurements and extend the simulation principles based on memristors to CRS devices and, hence, provide an analytical approach to the design of a CRS array. The presented approach creates the necessary design methodology platform that will assist designers in implementation of CRS devices in future systems.

The fourth element: Insights into the memristor

New developments in nanoelectronics are promising a new generation of computing, which has greater focus on device capabilities. Further to many applications of memristors in artificial intelligence or artificial biological systems, they enable reconfigurable nanoelectronics and also provide new paradigms in application specific integrated circuits (ASIC) and field programmable gate arrays (FPGA). Providing a significant reduction in area and an unprecedented memory capacity and device density are the potential features memristors for Integrated Circuits (IC). This work reviews the memristor and its characteristics and provides a SPICE macro-model of the memristors which helps us to develop models for the SPICE based circuit analysis tools like HSpice and Spectre. An insight into the memristor device recalling the quasi-static expansion of Maxwells equations and a review on Chuas argumentation about the memristor through the electromagnetic theory are also given.

An analog implementation of early visual processing in insects

An analog VLSI implementation which mimics the early visual processing stages in insects is described. The system is composed of sixty parallel channels of integrated photodetectors and processing elements. It serves as the front end processor for a motion detection chip. The photodetection circuitry includes p-well junction diodes on a 2 mu m CMOS process and a logarithmic compression to increase the dynamic range of the system. The processing elements consist of an analog differentiator behind each photodetector. The differentiators are low frequency and have been designed using subthreshold design methods.<<ETX>>

Fabrication and modeling of Ag/TiO 2 /ITO memristor

The nanometer scale feature of memristor created a broad range of opportunities for innovative architectures. The nature of the boundary conditions, the complexity of the ionic transport and tunneling mechanism, and the nanoscale feature of the memristor introduces new challenges in modeling, characterization, and measurements for Memristor-MOS (M2) circuits. These new challenges can be addressed by a joint insight from the circuit designer and device engineers, which will dictate the needed modeling and layout rules to attain an accurate estimation of M2 circuit performance. In this paper, memristive behavior of titanium dioxide (TiO2) is studied using a novel combination of electrodes, silver (Ag) and indium thin oxide (ITO). Fabrication method and a modeling approach are also explained. The ITO electrode provide (a) an excellent transparency in visible light, (b) improved functional reproducibility, and (c) non-volatile characteristics as well as a promising unique application of the M2 circuits in sensory applications. Furthermore, proposed modeling approach shows a good agreement between measurements and simulations of analog memory characteristics and reproducibility as well as long-term retention.

3-D System-on-System (SoS) Biomedical-Imaging Architecture for Health-Care Applications

This paper presents the implementation of a 3-D architecture for a biomedical-imaging system based on a multilayered system-on-system structure. The architecture consists of a complementary metal-oxide semiconductor image sensor layer, memory, 3-D discrete wavelet transform (3D-DWT), 3-D Advanced Encryption Standard (3D-AES), and an RF transmitter as an add-on layer. Multilayer silicon (Si) stacking permits fabrication and optimization of individual layers by different processing technology to achieve optimal performance. Utilization of through silicon via scheme can address required low-power operation as well as high-speed performance. Potential benefits of 3-D vertical integration include an improved form factor as well as a reduction in the total wiring length, multifunctionality, power efficiency, and flexible heterogeneous integration. The proposed imaging architecture was simulated by using Cadence Spectre and Synopsys HSPICE while implementation was carried out by Cadence Virtuoso and Mentor Graphic Calibre.

Memristor-CMOS logic and digital computational components

With the advent of memristor-CMOS (MCM) process that combines CMOS processing with nano-scale memristive devices, it becomes possible to reduce utilization of silicon area thus providing a promising option in the design of MCM based circuits. Two properties of memristor have attracted the most attention. Firstly its nanometer scale dimensions and, secondly, its nonvolatile memory characteristics. The nanometer scale feature of the device creates a new opportunity for new logic elements allowing realization of innovative circuits that are removed from the more established design domains. The non-volatile memory property enables us to realize new design methods for a variety of computational elements that lead to novel architectures. In this paper, we present primitive logic blocks based on MCM design style those are also extended to special logic types like Domino logic and programmable logic array (PLA). We also provide an overview of modeling principles that would allow designers to venture into this new integrated domain. Graphical abstractDisplay Omitted HighlightsWe introduce challenges in modeling and characterization for Memristor-CMOS (MCM) circuits.Memristor was fabricated with MIM structure based on Ag/TiO2-x/TiO2/ITO nano layers.The paper presents logic design methodologies for MCM design style.MCM enables multi-layer realization of the more complex circuits and future systems.

Obstacle avoidance and motion-induced navigation

In nature, the visual detection of motion appears to be used in a variety of tasks, ranging from collision avoidance to posture maintenance. Many insects seem to rely primarily on information provided by an array of elementary movement detectors in order to navigate. Moreover, experimental evidence suggests that motion information is interpreted at an early stage of the insect visual system, and may be closely linked to motor control. A motion detector, whose design is based on some of the characteristics of the insect visual system, has been implemented on a single VLSI chip. This paper shows the manner in which motion information, provided by the chip in real-time, may be utilised by the control system of an autonomous vehicle in low-level perceptual tasks.