Gang-Jun Kim

Effect of dynamic stress on off leakage of small-dimension pMOSFETs at high temperature

The degradation of the off leakage current Ioff in small-dimension pMOSFETs is investigated experimentally while applying a dynamic stress to the pMOSFETs. During the OFF-state stress, the dynamic stress induced an increase of Ioff due to generation of negative oxide charges Nox in the gate dielectric, and in the shallow trench isolation (STI) near the gate edge. When channel width W decreased, negative Nox in STI increase Ioff significantly, and the degradation of Ioff is more critical than degradation of Vth. These observations indicate that the effect of the dynamic stress in pMOSFETs on Ioff should be seriously considered when evaluating small-dimension pMOSFETs.

Method to extract parameters of power law for nano-scale SiON pMOSFETs under negative bias temperature instability

Abstract This paper proposes a fast and accurate method to extract parameters of the power law for nano-scale SiON pMOSFETs under negative bias temperature instability (NBTI), which is useful for an accurate estimation of NBTI lifetime. Experimental results show that accurate extraction of the time exponent n of the power law was obstructed by either fast trapping of minority carriers or damage recovery during measurement of threshold voltage V th . These obstructing effects were eliminated using Δ V th s obtained from fast and slow measurement-stress-measurement (MSM) procedures. The experimental SiON pMOSFETs had n  ≈ 1/4, an activation energy E a  = 0.04 eV for the fast recoverable degradation, and E a  = 0.2 eV for the slow permanent degradation. Based on these experimental observations, a method to estimate NBTI lifetime is proposed.

Effect of DC/AC stress on the reliability of cell capacitor in DRAM

Abstract The influence of DC and AC stress on leakage current Ileak of cell capacitor was analyzed. Experimental results indicated that DC stress induced the asymmetric damage of cell capacitor and increase of Ileak due to the increase of trap assisted emission electron, AC stress induced the damage on both nodes of capacitor and increase of Ileak due to formation of tunneling path in dielectric when AC stress was applied. At stress voltage VD1 ≥ 2.1 V, lifetime under AC stress was much worse that under DC stress, but the guaranteed voltage under AC stress at 10 years was twice as large as that under DC stress due to the difference of acceleration constant factor between DC and AC. As these results, the increase of Ileak under DC stress should be considered more important than that of AC stress for reliability estimation of cell capacitor as operating voltage decreases.

Effect of OFF-state stress on reliability of nMOSFET in SWD circuits of DRAM

Abstract In this paper, we investigate the effect of OFF-State stress occurring at nMOSFET in a sub word-line driver (SWD) circuit under the DRAM operating conditions. Through the experimental study, we found that the increase in the number of OFF-carriers by the OFF-State stress caused the significant decrease of ON-current (Ion). During the initial period, the OFF-State stress generated the positive oxide charges (Qox) and the interface traps (Nit), which caused the increase of OFF-current (Ioff) and the decrease of Ion. After the degradations were saturated, both the Ion and Ioff decreased due to the increase in the number of OFF-carriers. Also the OFF-State degradation increased with decreasing source voltage, channel doping concentration, and channel length. Furthermore, the sensitivity of the OFF-State degradation to body bias (Vb) increased with scaling the oxide thickness (Tox). These new observations suggest that the OFF-State degradation for core transistors can impose the significant limitation on the SWD circuit design in DRAM such as scaling of dimension and determination of word-line voltage.

Method of estimating mechanical stress on Si body of MOSFET using drain–body junction current

A simple and accurate method of estimating the mechanical stress σ on the Si body of a MOSFET is proposed. This method measures the doping concentration of the body, N d, and the onset voltage V hl for the high-level injection of the drain–body junction, uses N d, the ideality factor η, and the Fermi potential f ≈ V hl/2η to calculate the intrinsic carrier concentration n i of the Si body, and then uses the calculated n i to obtain the bandgap energy E g of the Si body. σ is estimated from E g using the deformation potential theory. The estimates of σ agree well with those obtained using previous methods. The proposed method requires one MOSFET, whereas the others require at least two MOSFETs, so the proposed method can give an absolute measurement of σ on the Si body of a MOSFET.

Channel width dependence of AC stress on bulk nMOSFETs

Abstract Channel width dependence of AC stress was investigated. OFF-state stress generated negative interface traps, positive oxide charges, and neutral traps in the whole channel region. Comparison of drain currents of parasitic and main MOSFET during OFF-state indicates that more defects were generated on channel edge than near its center. During ON-state stress, electrons were dominantly trapped in the neutral traps near channel edge. These results cause degradation due to AC stress to become increasingly severe as W is scaled down. The operating voltage to guarantee 10-year lifetime decreased as width decreased. The above results show that electron trapping in neutral traps near the channel edge induce severe degradation on narrow nMOSFET during AC stress. Therefore, degradation of channel edge during AC stress is an importantly considered in narrow nMOSFET.

Method to predict length dependency of negative bias temperature instability degradation in p-MOSFETs

We propose a method to predict the length dependency of the magnitude of degradation caused by negative bias temperature instability (NBTI) stress applied to a p-MOSFET. Threshold voltage degradation ?V th varied according to the drain bias V d, during the measurement of drain current I d. The depletion length L dep into the channel was calculated based on a particular V d value and the channel doping concentration. L dep was used to extract the channel edge region length L edge, then the center channel region length L cen was obtained by subtracting L edge from the gate length L gate. We proposed an equation that uses L dep, L cen, L edge and degree of ?V th variation to calculate ?V th according to L gate while the p-MOSFET is under NBTI stress. Equation estimates of ?V th at different L gate were similar to measurements.

Effect of dynamic stress on OFF leakage of nanoscale pMOSFETs at high temperature

This paper investigates the degradation of the off leakage current Ioff under a dynamic stress which appears in nanoscale pMOSFETs. Experimental results showed that OFF-state stress in the dynamic stress generated negative oxide charges Nox in a drain edge and a shallow trench isolation(STI). Nox was the dominant cause of the shift of Ioff ∆Ioff, and ∆Ioff increased when channel length L was short. Moreover Nox in the STI was hard to recover. As a result, Ioff under the dynamic stress increases significantly at the short channel pMOSFET. These observations indicate that the effect of the dynamic stress in pMOSFETs on Ioff increases with scaling down of L. Thus, the dynamic stress in pMOSFETs should be seriously considered when evaluating the short channel pMOSFETs.

Effect of negative bias temperature instability induced by a low stress voltage on nanoscale high-k/metal gate pMOSFETs

Abstract The effect of a low stress voltage on the negative bias temperature instability degradation in a nanoscale p -channel metal–oxide–semiconductor field-effect transistor using high- k /metal gate stacks is investigated. The direct current–current voltage and carrier separation methods are used to separate the effects of electrons and holes. The results indicate that a high stress voltage generates positive oxide charges that degrade the device, but a low stress voltage generates negative oxide charges that induce the turn-around effect of the threshold voltage.

Effect of electron–electron scattering at an elevated temperature on device lifetime of nanoscale nMOSFETs

Abstract The effect of electron–electron scattering (EES) on a nanoscale n-channel metal–oxide–semiconductor field-effect transistor was investigated. Experimental results indicate that EES stress creates more interface states and negative oxide charges than does channel hot-carrier (CHC) stress. Moreover, shifts of gate induced drain leakage current and substrate current confirm that defects generated by EES are distributed in the channel and drain region. Thus, the worst case hot carrier stress condition should be modified from CHC stress to EES stress.