Seonhaeng Lee

Influence of wall charge on image sticking phenomena in AC plasma display panels

Abstract This paper investigates the image sticking phenomenon in an AC plasma display panel (PDP), which appears when the PDP is subjected to a strong sustain discharge for an extended time and leaves a residual image on the display. This problem is very difficult to resolve using a conventional reset. Image sticking was investigated by observing the light emission from the reset, indicating that the wall charges accumulated on the sustain electrodes were the major cause. A few face (plate-gap) discharges equated the wall voltages on the sustain electrodes and set all cells of the PDP at the same external voltage for firing a surface discharge. The image sticking phenomenon disappeared after the face discharges.

Floating single sustain drive method for AC plasma display panel

This paper presents a method for driving an AC plasma display panel (PDP). This method separates the circuit ground for the sustain pulse generator from the system ground during the sustain period, so it is named the floating single sustain method. The problems observed in previous single sustain methods are solved by separating the ground systems. A drive waveform and circuit for the floating single sustain method are proposed, and a cost-effective method of connecting the drive circuit to the electrodes of a PDP is presented. Experimental results on a 42-in. WVGA single-scan PDP show that the proposed waveform and circuit are well suited for driving the PDP; all problems observed in the previous single sustain method are solved and the power consumption due to the sustain power leakage to the data drive circuit is eliminated.

Versatile energy recovery circuit for driving AC plasma display panel with single sustain circuit board

This paper presents an energy recovery (ER) circuit which can operate either in a series or a parallel resonance mode and can drive an AC plasma display panel (PDP) with a single sustain circuit board. The proposed ER circuit consists of one energy storage capacitor, two energy recovery inductors, and three insulated-gate bipolar transistors. The circuit operations in the series and parallel resonance modes are similar to conventional ones, except for the leading edge of the first sustain pulse and the trailing edge of the last sustain pulse. To reduce power consumption in the parallel resonance mode of operation, these two pulse edges are generated using a series resonance between the panel capacitance and the energy recovery inductor. The proposed circuit had energy recovery efficiencies in both the series and parallel resonance modes that were nearly the same as the efficiency of the conventional series resonance ER circuit. Experimental results on a 42-inch XGA single-scan PDP show that the proposed ER circuit is suitable for use in a PDP drive circuit.

Effect of La2O3 Capping Layer Thickness on Hot-Carrier Degradation of n-Channel Metal-Oxide-Semiconductor Field-Effect Transistors with High-k/Metal Gate Stacks

The effect of La2O3 capping layer thickness on the hot-carrier degradation of n-channel metal–oxide–semiconductor field-effect transistors (n-MOSFETs) with high-k/metal gate stacks is investigated. The hot-carrier degradation is monitored by measuring the threshold voltage Vth, transconductance gm, and subthreshold slope SS. As the thickness of the La2O3 layer increases, Vth degradation is enhanced regardless of whether the La2O3 layer is deposited above or below the HfSiO layer. The generation of interface traps induced by hot-carrier stress is intensified with an increase in the bottom capping layer thickness. On the other hand, the generation of oxide traps induced by hot-carrier stress is intensified with an increase in the top capping layer thickness.

Saturation of threshold-voltage shift during positive bias temperature instability in HfSiON/SiO2 n-channel MOSFET and its effect on device lifetime evaluation

This paper investigates the saturation of threshold-voltage shift ΔVth of HfSiON/SiO2 n-channel MOSFETs (nMOFSETs) under positive bias temperature instability (PBTI) and proposes an empirical PBTI degradation model that can predict operational lifetime tL accurately. Experimental results indicate that secondary-hole trapping occurred in the bulk dielectric due to hole injection at the anode after electron trapping in the initial bulk trap. This secondary-hole trapping causes a decrease in the time exponent n of the power law ΔVth ∝ tn as the gate stress voltage Vg,str increases. This dependency of n on Vg,str results in overestimation of tL when it was estimated using the conventional method which assumes a constant value of n. An empirical model that considers the effect of Vg,str on n is proposed; this model predicted operational tL = 2.6 × 105 s, which agreed well with experimentally-measured tL = 3.9 × 105 s.

Effect of negative bias temperature instability induced by a low stress voltage on nanoscale high-k/metal gate pMOSFETs

Abstract The effect of a low stress voltage on the negative bias temperature instability degradation in a nanoscale p -channel metal–oxide–semiconductor field-effect transistor using high- k /metal gate stacks is investigated. The direct current–current voltage and carrier separation methods are used to separate the effects of electrons and holes. The results indicate that a high stress voltage generates positive oxide charges that degrade the device, but a low stress voltage generates negative oxide charges that induce the turn-around effect of the threshold voltage.

Effect of electron–electron scattering at an elevated temperature on device lifetime of nanoscale nMOSFETs

Abstract The effect of electron–electron scattering (EES) on a nanoscale n-channel metal–oxide–semiconductor field-effect transistor was investigated. Experimental results indicate that EES stress creates more interface states and negative oxide charges than does channel hot-carrier (CHC) stress. Moreover, shifts of gate induced drain leakage current and substrate current confirm that defects generated by EES are distributed in the channel and drain region. Thus, the worst case hot carrier stress condition should be modified from CHC stress to EES stress.

Enhanced degradation of n-MOSFETs with high-k/metal gate stacks under channel hot-carrier/gate-induced drain leakage alternating stress

Abstract Enhanced degradation of n-MOSFETs with high-k/metal gate stacks under CHC/GIDL alternating stress is investigated. CHC stress generates negative oxide charges while GIDL stress generates positive oxide charges in the gate oxide near drain region. Theses oxide charges degrade device reliability, and degradation is enhanced when CHC stress and GIDL stress are applied alternatively. The degradation under CHC/GIDL alternating stress is due to the neutral traps and interface traps, and increases with the increase in frequency.