Gaofei Tang

Low On-Resistance Normally-Off GaN Double-Channel Metal–Oxide–Semiconductor High-Electron-Mobility Transistor

A low on-resistance normally-off GaN double-channel metal-oxide-semiconductor high-electronmobility transistor (DC-MOS-HEMT) is proposed and demonstrated in this letter, which features a 1.5-nm AlN insertion layer (ISL) located 6 nm below the conventional barrier/GaN interface, forming a second channel at the interface between the AlN-ISL and the underlying GaN. With gate recess terminated at the upper channel, normally-off operation was obtained with Vth of +0.5 V at IDS = 10 μA/mm or +1.4 V from the linear extrapolation of the transfer curve. The lower heterojunction channel is separated from the etched surface in the gate region, thereby maintaining its high field-effect mobility with a peak value of 1801 cm2/(V·s). The on-resistance is as small as 6.9 Q·mm for a DC-MOS-HEMT with LG/LGS/LGD = 1.5/2/15 μm, and the maximum drain current is 836 mA/mm. A high breakdown voltage (>700 V) and a steep subthreshold swing of 72 mV/decade are also obtained. Index Terms-Double-channel MOS-HEMT (DC-MOSHEMT), field-effect mobility, gate recess, normally-off.

Integration of LPCVD-SiN x gate dielectric with recessed-gate E-mode GaN MIS-FETs: Toward high performance, high stability and long TDDB lifetime

By employing an interface protection technique to overcome the degradation of etched GaN surface in high-temperature process, highly reliable LPCVD-SiN<inf>x</inf> gate dielectric was successfully integrated with recessed-gate structure to achieve high-performance enhancement-mode (V<inf>th</inf> ∼ +2.37 V @ I<inf>d</inf> = 100 μA/mm) GaN MIS-FETs with high stability and high reliability. The LPCVD-SiN<inf>x</inf>/GaN MIS-FET delivers remarkable advantages in high Vth thermal stability, long time-dependent gate dielectric breakdown (TDDB) lifetime and low bias temperature instability (BTI).

Enhancement-mode GaN double-channel MOS-HEMT with low on-resistance and robust gate recess

An enhancement-mode GaN double-channel MOS-HEMT (DC-MOS-HEMT) was fabricated on a double-channel heterostructure, which features a 1.5-nm AlN layer (AlN-ISL) inserted 6 nm below the conventional barrier/GaN hetero-interface, forming a lower channel at the interface between AlN-ISL and the underlying GaN. With the gate recess terminated at the upper GaN channel layer, a positive threshold voltage is obtained, while the lower channel retains its high 2DEG mobility as the heterojunction is preserved. The fabricated device delivers a small on-resistance, large current, high breakdown voltage, and sharp subthreshold swing. The large tolerance for gate recess depth is also confirmed by both simulation and experiment.

An Analytical Model for False Turn-On Evaluation of High-Voltage Enhancement-Mode GaN Transistor in Bridge-Leg Configuration

Compared with the state-of-the-art Si-based power devices, enhancement-mode Gallium Nitride (E-mode GaN) transistors have better figures of merit and exhibit great potential in enabling higher switching frequency, higher efficiency, and higher power density for power converters. The bridge-leg configuration circuit, consisting of a controlling switch and a synchronous switch, is a critical component in many power converters. However, owing to the low threshold voltage and fast switching speed, E-mode GaN devices are more prone to false turn-on phenomenon in bridge-leg configuration, leading to undesirable results, such as higher switching loss, circuit oscillation, and shoot through. In order to expand gate terminals safe operating margin without increasing reverse conduction loss during deadtime, negative gate voltage bias for turn-off and antiparallel diode could be applied to E-mode GaN device. In this paper, with consideration of strong nonlinearities in C–V and I–V characteristics of high-voltage (650 V) E-mode GaN transistors, analytical device models are first developed. Then, we develop an analytical circuit model that combines the circuit parameters with intrinsic characteristics of the high-voltage GaN transistor and antiparallel diode. Thus, key transient waveforms with regard to the false turn-on problem can be acquired, including displacement current and false triggering voltage pulse on gate terminal. The simulated waveforms are then verified on a testing board with GaN-based bridge-leg circuit. In contrast to piecewise switching process models and PSpice simulation, the proposed model exhibits outstanding performances. To provide design guidelines for mitigating false turn-on of GaN transistor, the impacts of different circuit parameters, along with the optimum negative gate voltage bias, are investigated based on the proposed model.

Characterization of Static and Dynamic Behaviors in AlGaN/GaN-on-Si Power Transistors With Photonic-Ohmic Drain

In this paper, static and dynamic performances of an AlGaN/GaN-on-Si power FET utilizing the integrated photonic-ohmic drain (PODFET) were systematically investigated. The operational mechanisms of the PODFET, including both the conditions of photon generation and the related physical processes, were explained. The dynamic switching tests were carried out under two types of hard switching conditions. With the photon generation and channel current inherently switched ON and OFF in synchronization, the dynamic performances of the PODFET can be significantly enhanced owing to photon pumping of deep electron traps. In addition, the generated photons were proved to be confined in proximity of the drain terminal without causing adverse effects on the device performances (e.g., the OFF-state leakage degradation).

Enhanced Dielectric Deposition on Single-Layer MoS2 with Low Damage Using Remote N2 Plasma Treatment

Using remote N2 plasma treatment to promote dielectric deposition on the dangling-bond free MoS2 is explored for the first time. The N2 plasma induced damages are systematically studied by the defect-sensitive acoustic-phonon Raman of single-layer MoS2, with samples undergoing O2 plasma treatment as a comparison. O2 plasma treatment causes defects in MoS2 mainly by oxidizing MoS2 along the already defective sites (most likely the flake edges), which results in the layer oxidation of MoS2. In contrast, N2 plasma causes defects in MoS2 mainly by straining and mechanically distorting the MoS2 layers first. Owing to the relatively strong MoS2-substrate interaction and chemical inertness of MoS2 in N2 plasma, single-layer MoS2 shows great stability in N2 plasma and only stable point defects are introduced after long-duration N2 plasma exposure. Considering the enormous vulnerability of single-layer MoS2 in O2 plasma and the excellent stability of single-layer MoS2 in N2 plasma, the remote N2 plasma treatment shows great advantage as surface functionalization to promote dielectric deposition on single-layer MoS2.

High-performance fully-recessed enhancement-mode GaN MIS-FETs with crystalline oxide interlayer

In this work, we developed an effective technique to form a sharp and stable crystalline oxidation interlayer (COIL) between the reliable LPCVD (low pressure chemical vapor deposition)-SiNx gate dielectric and recess-etched GaN channel. The COIL was formed using oxygen-plasma treatment, followed by in-situ annealing prior to the LPCVD-SiNx deposition. The COIL plays the critical role of protecting the etched GaN surface from degradation during high-temperature (i.e. at ∼ 780 °C) process, which is essential for fabricating enhancement-mode GaN MIS-FETs with highly reliable LPCVD-SiNx gate dielectric and fully recessed gate structure. The LPCVD-SiNx/GaN MIS-FETs with COIL deliver normally-off operation with a Vth of 1.15 V, small on resistance, thermally stable Vth and low positive-bias temperature instability (PBIT).

An analytical model for false turn-on evaluation of GaN transistor in bridge-leg configuration

Gallium Nitride (GaN) transistors are especially attractive in their capability of switching at high frequencies, and enable power conversion systems with reduced size and higher efficiency. However, owing to the low threshold voltage of the commercially available enhancement-mode (E-mode) GaN devices, the devices are more prone to false turn-on phenomenon, leading to larger switching losses, circuit oscillation and even shoot-through in bridge-leg configuration. In order to enlarge the gate terminals safe operating margin without increasing the reverse conduction loss during dead-time, a negative gate voltage bias for turn-off and an anti-parallel diode can be applied to GaN transistor. In this work, to accurately evaluate the detailed turn-on characteristics of GaN transistors in bridge-leg configuration, analytical device models that count for the strong nonlinearities of devices I-V and C-V characteristics are firstly developed. Then an analytical circuit model taking into account the circuit parameters as well as the intrinsic behaviors of GaN transistor and anti-parallel diode is established. Thus, the critical transient waveforms, such as displacement currents and false triggering voltage pulse on gate terminal can be simulated. The proposed models are then verified on a testing board with GaN-based bridge-leg circuit. To provide design guidelines for suppressing false turn-on, impacts of circuit parameters are investigated based on the proposed model.

Impact of substrate termination on dynamic performance of GaN-on-Si lateral power devices

Dynamic ON-resistance (äon) behaviors of 600-V GaN-on-Si lateral power devices with grounded and floating substrate termination are studied. It is found that the floating substrate termination not only enables higher OFF-state breakdown voltage, but also delivers the benefit of smaller dynamic Ron degradation under higher drain bias (> 400 V) switching operations. Under medium drain bias (< 300 V) switching, a moderately larger dynamic Ron degradation is resulted from a floating substrate. The underlying physical mechanisms are explained by charge storage in the Si substrate and electron trapping effect in the GaN buffer layer.

Impact of integrated photonic-ohmic drain on static and dynamic characteristics of GaN-on-Si heterojunction power transistors

In this work, static and dynamic characteristics of an AlGaN/GaN-on-Si power field-effect transistor (FET) with the integrated photonic-ohmic drain (POD) were systematically investigated. With the photon generation and channel current inherently switched ON and OFF in synchronization, dynamic performances (e.g. dynamic ON-resistance) of the PODFET can be significantly enhanced owing to photon pumping of deep electron traps. It is shown that the photons responsible for photon pumping of deep traps were confined in the proximity of the drain terminal without causing adverse effects on the device static performances (e.g. the OFF-state leakage degradation). Furthermore, the POD structure featured a robust tuning capacity on both breakdown voltage and threshold channel current for photon generation to the AlGaN/GaN power FET.