Garo Jacques Derderian

Elimination of Tungsten-voids in middle-of-line contacts for advanced planar CMOS AND FinFET technology

As dimension of middle-of-line contacts scale down, the Tungsten (W) gap-fill capability is critical, and we started to see function failure in SRAM and logic circuit caused by W-voids. We had observed that formation of W-voids is related to the contact profile, nucleation/barrier on sidewall, and deposition methods. Furthermore, even those initially “good” W-plugs are formed, the subsequent process steps may damage the W-plug and cause voids. These W voids lead to high resistance and failures in logic and SRAM circuit (see Fig.1). We analyzed mechanisms and illustrated solutions systematically with in-line detection method. We also discussed these solutions for technology development as well as manufacturing in this paper.

Understanding process and design systematics: Case study on monitoring strategy and understanding root cause of fin defectivity

As design rules shrink, semiconductor manufacturing becomes more complex which leads to a huge increase in the defects which could cause a non-yielding die. Process control and inline defect analysis becomes widely relevant to help shorten the learning process from R&D to production. This paper discusses the various methodologies which leverage patterned wafer inspection tools to help analyze defect mechanisms and figure out an inline process monitor to drive defect reduction and control. A defect example from FinFETs is used throughout the paper, demonstrating the clever use of design grouping and design based inspected areas. These helped to determine the root cause of the problem of systematics in FinFET and also created a monitoring strategy for the same. The results support the effectiveness of the tools by helping to reduce defectivity in the FinFET module and also creating a process monitor which can filter large numbers of defects to provide timely process learning.