Min-Hwa Chi

A High Resolution Cmos Imager With Active Pixel Using Capacitively Coupled Bipolar Operation

The active pixel sensor technology promises high performance than conventional CCD imagers. This paper reports a new high resolution CMOS imager with one transistor active pixel sensing based on capacitor-coupled bipolar action. The base capacitor is pulsed negatively for image integration and positively for image sensing. The pixel size is 5.9um x 5.9um (on 0.8um design rule). The prototype imager has an array of 480 x 640 and operating at 5v Vcc. This active pixel structure is promising for future high-performance and high-density imagers in the information highway era.

True low-voltage flash memory operations

This paper proposes true low-voltage operations for high-performance flash memory. The program and erase operations only need voltages not exceeding the junction breakdown voltage of CMOS technology. In this way, flash memory is easily integrated with CMOS logic circuits, since there is no special fabrication process for high-voltage junctions, gate oxide, and field isolation. Low-voltage programming is based on hot electron injection with Vcc on drain and gate. Low-voltage erase is based on Fowler-Nordheim (F-N) tunneling with negative gate bias and Vcc on source and careful grounding the n-well for negative voltage circuits. Low-voltage read operation is seriously degraded using conventional one-transistor (1T) cell due to reduced read current by low gate bias and not allowing operation in depletion. A 2-transistor (2T) cell structure is proposed for high speed read at low Vcc by allowing cell operation in depletion, precharging the cell gate, and switching the select transistor by Vcc. This scheme greatly simplifies the cost of integrating flash memory with logic circuits and is promising for future high-performance systems with low-voltage and low-power applications.

Low-voltage multi-level flash memory: determination of minimum spacing between multi-levels [CMOS]

This paper reports that cell reliability issues (e.g. V/sub T/ spread, program disturb, read disturb, subthreshold leakage current, and charge retention), read scheme, and cell structures are the factors for minimizing V/sub T/ spacing for multi-level storage in flash memory. A 2T cell structure is proposed for wider V/sub T/ window, high speed read, and smaller V/sub T/ spacing in order to store more V/sub T/ levels than 1T cell.