Gary K. Maki

Fault-Tolerant Asynchronous Sequential Machines

A general design technique for achieving single fault-tolerant asynchronous sequential circuits is described. The design procedures apply over a large range of fault conditions and are extremely easy to use. Generally, less than three times the logic required for a single copy is needed to achieve single fault tolerance. In addition to fault tolerance, real time fault detection is easily achieved and it is immediately known when single fault tolerant capability is exceeded.

Pass-transistor asynchronous sequential circuits

Design methods for asynchronous sequential pass-transistor circuits, which result in circuits that are hazard- and critical-race-free and which have added degrees of freedom for the input signals, are discussed. The design procedures are straightforward and easy to implement. Two single-transition-time state assignment methods are presented, and hardware bounds for each are established. A surprising result is that the hardware realizations for each next state variable and output variable is identical for a given flow table. Thus, a state machine with N states and M outputs can be constructed using a single layout replicated N+M times. >

VLSI Reed Solomon Decoder Design

A Reed Solomon code is a highly efficient error correcting code that NASA will use in future space communication missions. A VLSI implementation of the decoder is presented that accepts data rates of 80Mbits/second. A total of 7 chips are needed and operate with the symbol clock being the system clock for the chip set. Approximately 1.65 billion Galois Field operations per second are achieved with this chip set.

A 320 Mbps flexible image data compressor for space applications

A 320 Mbps radiation-tolerant image data compression application specific integrated circuit (ASIC) chip set has been developed. 12The ASIC chip set implements the Consultative Committee for Space Data Systems (CCSDS) recommendation for Image Data Compression. It is applicable to both near-Earth push-broom3 sensors as well as frame sensors used in exploration and deep space applications. The compressor can process sensor data in both lossless and lossy compression modes.

Radiation hardening by design

Historically, specialized foundry processes have been utilized to produce radiation hardened microelectronics. Radiation hardness by design techniques have been shown to be capable of producing devices of sufficient hardness to resist the deleterious effects of the natural radiation environment of space utilizing standard commercial processes. A description of the nature of radiation effects in microelectronics is presented followed by design techniques effective in mitigating single event effects in both static memory cells and combinational logic. A formal method based on the theory of asynchronous sequential circuits is used to analyse memory cells for recovery properties. A dual rail n-channel metal oxide semiconductor (NMOS) structure with a cross coupled output buffer dramatically reduces the susceptibility of combinational logic to propagation of single event transients.

A novel homogeneous bioluminescence resonance energy transfer element for biomolecular detection with CCD camera or CMOS device

A novel optical signal element based on homogeneous bioluminescence resonance energy transfer (BRET) was developed for biomolecular detection. A fluorescent dye and alkaline phosphatase (AP) conjugate was used as a reporter and light-generation element for imaging detection platforms that use a CCD camera or CMOS chip-based devices. In the presence of a luminescence substrate, the energy from the first light emission of a bioluminescence enzymatic reaction was transferred to fluorescent dyes which were conjugated to an enzyme. This resulted in a second light emission with a shorter wavelength. The second light was localized at the position of target molecules without the diffusion problems present in current technology. To optimize energy transfer efficiency, the ratio of enzyme to fluorophore in the conjugates, the fluorescent dyes used in the conjugates and the luminescence substrates used for BRET were investigated. BRET was demonstrated by using both a CCD camera and a CMOS imaging device. Image spatial resolution was greatly improved compared with conventional chemiluminescence detection. This new signal element opens a door for the direct measurement of fluorescent signals on an imaging chip without an external light source and portable instrumentation normally required for the fluorescent detection of biomolecules.

Sequence-invariant state machines

A synthesis method and an MOS VLSI architecture are presented to realize sequential circuits that have the ability to implement any state machine having N states and m inputs, regardless of the actual sequence specified in the flow table. The design method utilizes binary tree structured logic to implement regular and dense circuits. The desired state sequence can be hardwired with power supply connections or can be dynamically reallocated if stored in a register. This allows programmable VLSI controllers to be designed with a compact size and performance approaching that of dedicated logic. Results of ICV implementations are reported and an example sequence-invariant state machine is contrasted with implementations based on traditional methods. >

An (8158,7136) low-density parity-check encoder

Low-density parity-check codes achieve coding performance which approaches the Shannon limit. Based on a novel method for deriving regular quasi-cyclic sub-codes, a radiation tolerant encoder was implemented in 0.25/spl mu/m CMOS. Use of generator polynomial reconstruction, partial product multiplication and functional sharing in the parity register results in a highly efficient design. Only 1,492 flip flops along with a programmable 21-bit look-ahead scheme are used to achieve a 1 Gb/s data throughput. A comparable two-stage encoder requires 8,176 flip flops.

VLSI asynchronous sequential circuit design

A novel design procedure for VLSI asynchronous sequential circuits is presented. It is based on partition algebra and generates circuits that use fewer transistors compared to previous procedures. This design procedure is simple and produces circuits that have very regular structures and are faster compared to the circuits generated by the existing procedures. This is due to the reduced number of transistors in the chain connected to the buffer. The circuits are generated by replication of similar units. This leads to a regular layout, and the small blocks can be optimized for optimum performance. This procedure can be extended to synchronous sequential machine design by replacing the buffer with a D flip-flop.<<ETX>>

Improved State Assignment Selection Tests

Critical race-free internal-state assignments can be found by several methods. Often these methods produce several assignments for the same flow table. New and improved tests are presented that can be used to select that assignment which is most likely to produce a set of simple design equations. These tests are applicable to the next-state equations as well as the output equations. The tests are applicable to circuits that are to be realized with NAND gates or set-reset (SR) flip-flops. Another advantage of these tests is that they allow comparison between state assignments with differing numbers of internal-state variables.