Sterling R. Whitaker

Circuit techniques for the radiation environment of space

Outer space provides a harsh environment for electronic circuits. Even near earth orbits are subject to radiation that can cause temporary upsets of logic states and long term performance degradation of integrated circuits. Catastrophic failure can also be caused by radiation when SCR latchup is induced by a heavy ion strike. This paper reports design techniques which harden MOS circuits against radiation effects in the space environment.

Low power radiation tolerant VLSI for advanced spacecraft

The combination of two synergistic VLSI technologies, ultra low power CMOS and radiation tolerant by design, offers an opportunity to provide advanced electronics capabilities for future spacecraft. The 500 mV CMOS process can yield orders of magnitude power reduction compared to current space-flight technologies and the radiation tolerance provides immunity against single event latch-up, good single event upset resistance and total ionizing dose immunity of at least 200 krads(Si). A study based on the EO-1 spacecraft requirements indicates that the use of these technologies could provide spacecraft power savings of 73% and total mass savings of 16%.

Pass-transistor asynchronous sequential circuits

Design methods for asynchronous sequential pass-transistor circuits, which result in circuits that are hazard- and critical-race-free and which have added degrees of freedom for the input signals, are discussed. The design procedures are straightforward and easy to implement. Two single-transition-time state assignment methods are presented, and hardware bounds for each are established. A surprising result is that the hardware realizations for each next state variable and output variable is identical for a given flow table. Thus, a state machine with N states and M outputs can be constructed using a single layout replicated N+M times. >

An 860-Mb/s (8158,7136) Low-Density Parity-Check Encoder

Low-density parity-check codes achieve coding performance which approaches the Shannon limit. An (8158,7136) encoder was implemented in a five-metal, 0.25-mum CMOS process. Use of generator polynomial reconstruction, partial product multiplication and functional sharing in the parity register results in a highly efficient design. Only 1492 flip-flops along with a programmable 21-bit look-ahead scheme are used to achieve an 860-Mb/s data throughput for this rate 7/8 LDPC code. A comparable two-stage encoder requires 8176 flip-flops

A 320 Mbps flexible image data compressor for space applications

A 320 Mbps radiation-tolerant image data compression application specific integrated circuit (ASIC) chip set has been developed. 12The ASIC chip set implements the Consultative Committee for Space Data Systems (CCSDS) recommendation for Image Data Compression. It is applicable to both near-Earth push-broom3 sensors as well as frame sensors used in exploration and deep space applications. The compressor can process sensor data in both lossless and lossy compression modes.

Radiation hardening by design

Historically, specialized foundry processes have been utilized to produce radiation hardened microelectronics. Radiation hardness by design techniques have been shown to be capable of producing devices of sufficient hardness to resist the deleterious effects of the natural radiation environment of space utilizing standard commercial processes. A description of the nature of radiation effects in microelectronics is presented followed by design techniques effective in mitigating single event effects in both static memory cells and combinational logic. A formal method based on the theory of asynchronous sequential circuits is used to analyse memory cells for recovery properties. A dual rail n-channel metal oxide semiconductor (NMOS) structure with a cross coupled output buffer dramatically reduces the susceptibility of combinational logic to propagation of single event transients.

An ultra-low-power, radiation-tolerant Reed Solomon encoder for space applications

Power is a limiting constraint in spacecraft design. This paper describes a Reed Solomon encoder designed for NASA using a triple metal, 0.35 /spl mu/m, ultra-low-power (500mV) CMOS process. Comparisons with a 3.3 V version show a 29.6 to 1 reduction in power to 14.3 mW at 60 MHz. Hardness against space radiation effects was achieved through circuit and layout techniques.

Sequence-invariant state machines

A synthesis method and an MOS VLSI architecture are presented to realize sequential circuits that have the ability to implement any state machine having N states and m inputs, regardless of the actual sequence specified in the flow table. The design method utilizes binary tree structured logic to implement regular and dense circuits. The desired state sequence can be hardwired with power supply connections or can be dynamically reallocated if stored in a register. This allows programmable VLSI controllers to be designed with a compact size and performance approaching that of dedicated logic. Results of ICV implementations are reported and an example sequence-invariant state machine is contrasted with implementations based on traditional methods. >

An (8158,7136) low-density parity-check encoder

Low-density parity-check codes achieve coding performance which approaches the Shannon limit. Based on a novel method for deriving regular quasi-cyclic sub-codes, a radiation tolerant encoder was implemented in 0.25/spl mu/m CMOS. Use of generator polynomial reconstruction, partial product multiplication and functional sharing in the parity register results in a highly efficient design. Only 1,492 flip flops along with a programmable 21-bit look-ahead scheme are used to achieve a 1 Gb/s data throughput. A comparable two-stage encoder requires 8,176 flip flops.

Self synchronized asynchronous sequential pass transistor circuits

A new class of CMOS VLSI asynchronous sequential circuits utilizing pass transistors is introduced. This class of self synchronizing circuits eliminates the need for critical race free state assignments. These circuits synchronize the transition path action by forcing the circuit to sequence through proper unstable states. >