Gary L. Solbrekken

Analytical modeling of silicon thermoelectric microcooler

Due to its inherently favorable properties, doped single-crystal silicon has potential application as an on-chip thermoelectric microcooler for advanced integrated circuits. In this paper, an analytical thermal model for silicon microcooler, which couples Peltier cooling with heat conduction and heat generation in the silicon substrate, and which includes heat conduction and heat generation in the metal lead, is derived and used to study the thermal characteristics of silicon thermoelectric microcoolers. The analytical modeling results are shown to be in good agreement with the experimental data and the results from electrothermal numerical simulations. The effects of metal lead, electric contact resistance, silicon doping concentrations, and microcooler sizes on the cooling performance are investigated. The cooling potential of such thermoelectric devices, represented by peak cooling and maximum cooling heat flux on the microcooler surface, is addressed.

Thermoelectric-powered convective cooling of microprocessors

Forced convection cooling of a personal computer microprocessor, using power generated by thermoelectric (TE) conversion, has been modeled, analyzed, and demonstrated. This study was motivated by the desire to meet the demanding cooling requirements of notebook computers without consuming valuable battery power. The modest power generated by the TE necessitated a careful match between the TE device and the fan/heat-sink sub-system. The models and methodology used to maximize the cooling capability of TE-powered convection are presented and experimentally validated using a notebook computer prototype. In the experimental study described herein, a commercial fan was successfully driven by electricity generated from the heat of the microprocessor. It was determined that, at a junction temperature of 95 /spl deg/C, thermoelectric-powered cooling could perform nearly four times better than the best natural convection design.

Comprehensive system-level optimization of thermoelectric devices for electronic cooling applications

Advanced cooling solutions are needed to address the growing challenges posed by future generations of microprocessors. This paper outlines an optimization methodology for electronic system based thermoelectric (TE) cooling. This study stresses that an optimum TE cooling system should keep the electronic device below a critical junction temperature while utilizing the smallest possible heat sink. The methodology considers the electric current and TE geometry that will minimize the junction temperature. A comparison is made between the junction temperature minimization scheme and the more conventional coefficient of performance (COP) maximization scheme. It is found that it is possible to design a TE solution that will both maximize the COP and minimize the junction temperature. Experimental measurements that validate the modeling are also presented.

Chip Level Refrigeration of Portable Electronic Equipment Using Thermoelectric Devices

It is well established that the power dissipation for electronic components is increasing. At the same time, high performance portable equipment with volume, weight, and power limitations are gaining widespread acceptance in the marketplace. The combination of the above conditions requires thermal solutions that are high performance and yet small, light, and power efficient. This paper explores the possibility of using thermoelectric (TE) refrigeration as an integrated solution for portable electronic equipment accounting for heat sink and interface material thermal resistances. The current study shows that TE refrigeration can indeed have a benefit over using just a heat sink. Performance maps illustrating where TE refrigeration offers an advantage over an air-cooled heat sink are created for a parametric range of CPU heat flows, heat sink thermal resistances, and TE material properties. During the course of the study, it was found that setting the TE operating current based on minimizing the CPU temperature (Tj ), as opposed to maximizing the amount of heat pumping, significantly reduces Tj . For the baseline case studied, a reduction of 20–30°C was demonstrated over a range of CPU heat dissipation. The parametric studies also illustrate that management of the heat sink thermal resistance appears to be more critical than the CPU/TE interfacial thermal resistance. However, setting the TE current based on a minimum Tj as opposed to maximum heat pumping reduces the system sensitivity to the heat sink thermal resistance.Copyright

Thermoelectric Micro-Cooler for Hot-Spot Thermal Management

Driven by shrinking feature sizes, microprocessor “hot-spots” — with their associated high heat flux and sharp temperature gradients — have emerged as the primary “driver” for on-chip thermal management of today’s IC technology. Solid state thermoelectric micro-coolers offer great promise for reducing the severity of on-chip “hot-spots”, but the theoretical cooling potential of these devices, fabricated on the back of the silicon die in an IC package, has yet to be determined. The results of a three-dimensional electro-thermal finite-element modeling study of such a micro-cooler are presented. Attention is focused on the hot-spot temperature reductions associated with variations in micro-cooler geometry, chip thickness, and chip doping concentration, along with the parasitic Joule heating effects from the electrical contact resistance and current flow through the silicon. The modeling results help to define the optimum solid-state cooling configuration and reveal that, for the conditions examined, nearly 80% of the hot-spot temperature rise of 2.5°C can be removed from a 70μm × 70μm, 680W/cm2 hot-spot on a 50μm thick silicon die with a single micro-cooler.Copyright

Optimization of thermoelectric cooling for microelectronics

The electronics industry has traditionally cooled critical components using a simple fan/heat sink assembly. Each advance in IC fabrication technology has resulted in the need for a higher performance thermal solution, stressing the limits of conventional fan/heat sink technology. A possible solution to relieve the pressure being placed on future fan/heat sink technology is to incorporate thermoelectric (TE) cooling into the configuration. It has been established that when using TE technology in electronic applications the entire system needs to be optimized simultaneously. This study is an expansion of previous work as it provides an analytic expression for the TE element geometry that minimizes the junction temperature in an electronic application. Further, it is shown that a minimum junction temperature and a maximum COP can be simultaneously achieved by optimizing both the applied current and the TE geometry. Experimental measurements on commercial TE modules are presented that validate the 1-dimensional thermal-electric models. The measurements precisely match predictions if temperature dependent material properties are used in the models. A model based case study suggests that up to ~100 W can be dissipated using a 0.4 K/W heat sink and an optimized bismuth-telluride TE module while maintaining a 85 degC junction temperature

AN IMPROVED OPTIMIZATION APPROACH FOR THERMOELECTRIC REFRIGERATION APPLIED TO PORTABLE ELECTRONIC EQUIPMENT

The electronics industry has relied heavily on air cooling to dissipate waste heat. Each new generation of technology is smaller and more powerful, pushing the limits of air-cooled heat sinks. A competing constraint is that the thermal solutions need to be smaller and lighter, particularly for portable devices. A viable strategy to extend the limits of air-cooled heat sinks in a mass effective way is thermoelectric (TE) cooling. In general, the limiting COP of currently available TE materials requires that TE modules be operated at near optimum conditions. The conventional approach for optimizing TE modules ignores external irreversibilities, such as the heat sink temperature drop between the TE hot side and the ambient. The current study reviews two schemes for optimizing the operating current and compares their performance. The comparison between the COP maximizing current and the junction temperature minimizing current identifies where the two approaches yield the exact same performance. Performance regimes are then identified where the junction temperature minimizing approach provides an advantage over the COP maximizing approach. A significant extension of the current modeling activity over previous studies is allowing the TE module geometry to be optimized in addition to the operating current. When the TE module geometry is allowed to be optimized, it is found that using TE refrigeration operating at the junction temperature minimizing current will always have a performance benefit relative to a heat sink alone. The way this performance is achieved at higher heat loads is that the TE module elements must be made very thin.© 2005 ASME

Peltier Enhanced Heat Spreading for Localized Hot Spot Thermal Management

Localized areas of high heat flux on microprocessors are currently being identified as a dominant challenge for the thermal management community. Heat flux values up to 1 kW/cm2 prevailing over a fraction of the overall CPU surface area create local hot spots that need to be cooled. However, thermal solutions designed for the maximum heat flux overcool the rest of the CPU, wasting resources and creating large on-die temperature gradients. Wasting resources obviously has a negative economic and thermodynamic impact. However, it has been argued that large on-die temperature gradients reduce chip reliability and increase the difficulty in laying out the electric circuits. The current study proposes a strategy to reduce local hot spots by enhancing heat spreading through the use of the Peltier effect. The Peltier effect is most commonly associated with the operation of thermoelectric modules. In thermoelectric modules, heat is transported across the module by electrons. Ideally, the material used for the thermoelectric module would have a very low thermal conductivity to reduce the amount of back heat conduction through the thermoelectric elements, and the electric resistivity would be very low to minimize the Joule heating. Using today’s best commercially available thermoelectric materials, the thermal conductivity, electric resistivity, and Seebeck coefficient are such that the COP for the thermoelectric module is on the order of 1. This implies that in order to cool a processor dissipating 100W, an additional 100W of electric power must be supplied to the thermoelectric module. A total of 200W must then be rejected by the heat sink and any building HVAC system. A more pragmatic approach is to use the Peltier effect to not cool the entire CPU, but rather only the high heat flux region. This is accomplished by placing the thermoelectric elements laterally on the backside of the CPU. The cooling junction is placed in the proximity of the high flux region, while the heating junction is placed in contact with the CPU in low heat flux area that can tolerate the additional heat, effectively creating an active heat spreader. The Peltier enhanced heat spreading proposed here is shown to provide a reduction in the temperature of a localized hot spot relative to passive heat spreading. The amount of reduction in temperature depends on the thickness of the material as well as the thermal conductivity, but values up to 50% are illustrated.Copyright

Thermofluid Design of Energy Efficient and Compact Heat Sinks

A compact, energy efficient heat sink design methodology is presented for shrouded, parallel plate fins in laminar flow. The analytic model accounts for the sensible temperature rise of the air flowing between fins, convective heat transfer to the flowing stream, and conduction in the fins. To evaluate the efficiency of the air cooling system, consideration is also given to the determination of the fan pumping power. This paper focuses on the optimization of the heat sink-fan combination for energy efficiency, subject to volumetric constraints. The design optimum is found by matching the most efficient operating point of the fan with the corresponding optimum fin geometry. A series of parametric studies was completed to identify the sensitivity of the cooling solution to parametric variations. This numerically validated model has been used to visualize the parametric impact of dealing with “real world” manufacturing limitation in the development of thermal packaging solutions for notebook computers and other electronic products.© 2003 ASME

Assembly and Irradiation Modeling of Residual Stresses in Low-Enriched Uranium Foil-Based Annular Targets for Molybdenum-99 Production

This paper considers a composite cylindrical structure, with low-enriched uranium (LEU) foil enclosed between two aluminum 6061-T6 cylinders. A recess is cut all around the outer circumference of the inner tube to accommodate the LEU foil of open-cross section. To obtain perfect contact at the interfaces of the foil and the tubes, an internal pressure is applied to the inner tube, thereby plastically and elastically deforming it. The residual stresses resulting from the assembly process are used along with a thermal stress model to predict the stress margins in the cladding during irradiation. The whole process was simulated as a steady-state two-dimensional problem using the commercial finite element code Abaqus FEA. The irradiation behavior of the annular target has been presented, and the effect of the assembly residual stresses has been discussed.