Gary Lauterbach

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international solid-state circuits conference | 1998

Raymond A. Heald; Ken Shin; Vinita Reddy; I-Feng Kao; Masood Khan; William L. Lynch; Gary Lauterbach; Joe Petolino

This circuit combines a sum-addressed-memory (SAM) cache with delayed-reset logic circuitry, enabling cache access with a two-cycle-latency for a 6OO MHz third-generation superscalar processor implementing the Sparc V9 64b architecture.

international solid-state circuits conference | 2000

Gary Lauterbach; D. Greenley; S. Ahmed; M. Boffey; J. Chamdani; Si-En Chang; D. Chen; Yu Fang; K. Holdbrook; M. Hsieh; B. Keish; R. Melanson; C. Narasimhaiah; J. Petolino; Tung Pham; Le Quach; Kit Tam; Duong Tong; Liuxi Yang; Kui Yau

UltraSPARC-III (US-III) is a 64 b 800 MHz 4-instruction-issue superscalar microprocessor for high-performance desktop workstation, work group server, and enterprise server platforms. On-chip caches include a 64 kB 4-way associative for data, 32 kB 4-way associative for instructions, a 2 k B 4-way associative data prefetch cache, and a 2 kB 4-way associative write. A 90 kB on-chip tag array supports the off-chip 8 MB unified second-level cache. The 23 M-transistor chip in a 0.15 /spl mu/m, 7-layer metal process consumes 60 W from a 1.5 V supply.

Archive | 1999