Joseph Petolino
Sun Microsystems
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Featured researches published by Joseph Petolino.
ieee region 10 conference | 1989
Anant Agrawal; Emil W. Brown; Dave Murata; Joseph Petolino
The scalable processor architecture (SPARC) defines a general purpose 32 bit RISC processor architecture. The simple nature of the architecture provides a migration path to higher performance levels as new technologies become available. The goal was to design an architecture that would scale with, or track, improvements in the circuit technology. It has been implemented in gate arrays, full custom CMOS and bipolar emitter coupled logic (ECL) technologies by four different vendors. A number of implementations in other technologies including BiCMOS and GaAs are underway. A description is given of the B5000, the bipolar ECL implementation of the SPARC architecture. Also covered are some of the system level considerations that influenced the design of the processor.<<ETX>>
Archive | 1997
Joseph Petolino; William L. Lynch; Gary Lauterbach; Chitresh Chandra Narasimhaiah
Archive | 1996
Arthur T. Leung; Joseph Petolino
Archive | 1997
Joseph Petolino; William L. Lynch; Gary Lauterbach; Kalon S. Holdbrook
Archive | 1993
Joseph Petolino; Emil W. Brown
international symposium on microarchitecture | 1990
Emil W. Brown; Anant Agrawal; Trevor Creary; Michael F. Klein; Dave Murata; Joseph Petolino
Archive | 1997
Joseph Petolino
ieee computer society international conference | 1988
Anant Agrawal; Emil W. Brown; Joseph Petolino; James R. Peterson
Archive | 1997
Sanjay Vishin; Joseph Petolino
Archive | 1995
Joseph Petolino
