Gary W Ray

Interlevel dielectric failures in copper/low-k structures

Failure modes for inter-level dielectric layers under accelerated test conditions have been evaluated for a range of dielectric diffusion barriers in copper/low-k structures. The dominant failure mechanism for both constant voltage tests and ramped voltage tests was mechanical cracking at the dielectric barrier/low-k interface. Few occurrences of copper diffusion through the bulk ILD were observed. A simple model for the dominant failure mechanism is proposed which hypothesizes crack formation due to the electrostatic force between interdigitated lines followed by copper extrusion into the cracks. The proposed model is consistent with measurements of interfacial adhesion strengths in Cu/low-k stacks.

Thermal Stability of a-C:F,H Films Deposited by Electron Cyclotron Resonance Plasma Enhanced Chemical Vapor Deposition

Amorphous carbon films grown with fluorohydrocarbons can be grown to have dielectric constant values around 2.0. The behavior of these films when subjected to thermal excursion is studied. We have investigated material deposited in an ECR plasma, and find that the F:H ratio of the gas mixture is a good guide to material properties. Films deposited at 5°C were placed in a vacuum chamber at 400°C as long as 60 minutes. The film thickness, dielectric constant, and infrared absorption spectrum change with the F:H ratio of the incoming gas and thermal cycling. It was found that the dielectric constant and loss tangent decrease upon heating and that there is an apparent increase in C=C groups. As expected, as the F:H ratio increases, the dielectric constant and thermal stability decrease. Good thermal stability is shown for F:H ratios of 1.5, which result in films with a dielectric constant of ∼2.4 after heating.

Low Dielectric Constant Materials Integration Challenges

Considerable effort has been expended in recent years in the development, evaluation, and integration of new low Kc dielectric materials for IC applications. Many film properties must be measured before a film can be selected for integration into an interconnect process flow. Among them are glass transition temperature, thermal stability, Youngs modulus, adhesion, stress, coefficient of thermal expansion, dielectric constant, breakdown voltage, solvent resistance, dry etch characteristics, and gap fill performance. These properties must in turn be considered when developing interconnect process modules and selecting the associated equipment set. The properties of these materials differ from those of the commonly used (PE)CVD silicon dioxides to varying extents, depending upon the nature of their composition and structure. This has often resulted in substantial modifications to the modules that comprise interconnect process flows, sometimes compromising manufacturability. This paper will address some of the issues associated with the integration of low K materials into interconnect process flows and how they are related to the properties of these materials.

Hydrogenated Amorphous Silicon Photodiode Technology for Advanced CMOS Active Pixel Sensor Imagers

Amorphous silicon photodiode technology is a very attractive option for image array integrated circuits because it enables large die-size reduction and higher light collection efficiency than c-Si arrays. We have developed a photodiode array technology that is fully compatible with a 0.35µm CMOS process to produce image sensors arrays with 10-bit dynamic range that are 30% smaller than comparable c-Si photodiode arrays. The VGA (640x480), array demonstrated here uses common intrinsic and p-type contact layers, and makes reliable contact to those layers by use of a monolithic transparent conductor strap tied to vias in the interconnect. The work presented here will discuss performance issues and solutions that lend themselves to cost-effective high-volume manufacturing. The various methods of interconnection of the diode to the array and their advantages will be presented. The photodiode dark leakage current density is about 80 pA/cm 2 , and its absolute quantum efficiency peaks about 85% at 550 nm. The effect of doped layer thickness and concentration on quantum efficiency, and the effect of a-Si:H defect concentration on diode performance will be discussed.

A Novel Statistical Metrology Framework for Identifying Sources of Variation in Oxide Chemical‐Mechanical Polishing

A statistical metrology framework is used to identify systematic and random sources of interlevel dielectric thickness variation. Electrical and physical measurements, technology computer-aided design simulations, design of experiments, signal processing, and statistical analysis are integrated via statistical metrology to deconvolve interlevel dielectric thickness variation into constituent variation sources. In this way, insight into planarization variation is enabled; for a representative chemical/mechanical polishing process, we find that die-level neighborhood interactions are comparable to die level feature dependent effects, and that within each die, die level variation is greater than wafer level variation. The characterization of variation sources via statistical metrology is critical for improved process control, interconnect simulation, and robust circuit design.

Mid-gap states measurements of low-level boron-doped a-Si:H films

Abstract Previous measurements of the effects of low-level boron-doping on a-Si:H thin films indicated that the conductivity decreased as a function of boron concentration. This effect was reinvestigated in this work by measuring the leakage current of stacked p–i–n diodes as a function of boron concentration. The supporting measurements employed films deposited onto insulating substrates. The diodes were also examined by a charge recovery measurement to measure the dangling-bond density of states (DOS) near between 0.7 and 1.0 eV from the conduction band edge. The spectrum shows a broad band with a peak at 0.88 eV, which increases as a function of the boron concentration, but does not shift with respect to energy. The dangling-bond density increase is proportional to the B2H6/SiH4 gas flow ratio, but not linear with respect to boron concentration in the film.

The effect of thermal cycling on a-C:F,H low dielectric constant films deposited by ECR plasma enhanced chemical vapor deposition

Thin films of a-C:F,H have been investigated to understand the effect of post-deposition annealing on density, dielectric constant, and composition. Although the initial dielectric constant value for the films was 3.2, the value decreased to about 2.4, and the loss tangent decreased from 0.12 to 0.03 after heating to 400/spl deg/C. Correspondingly, the film density decreased on the order of 10%, and an increase in the C=C content of the infrared spectra was observed. Most of these measured properties reached at least 75% of their final value within 5 minutes annealing. These results suggest that a more open film network is the basis of the lower dielectric constant.

100-nm CMOS gates patterned with 3 sigma below 10 nm

We have developed a process that uses a series of depositions and etches to pattern poly-silicon gates, eliminating the component of line width variation that normally arises from photolithography. Because the depositions and etches that determine line width are well controlled, we can pattern finer lines with better control using this process than with conventional methods. The results presented here show 3(sigma) < 10 nm for 100 nm lines. They are consistent with requirements for patterning gates in 2006 according to the 1997 edition of the National Technology Roadmap for Semiconductors. Using this patterning technique, we have made 100 nm nMOS transistors with 2 nm thick gate oxide, operating at 1.3 V. The distributions of important variables that characterize the operation of these transistors are shown to be much tighter than we obtain with conventional lithography.